r.

ANALOG
L.III DEVICES
CMOS
8 10-BitMonolithic
AID Converter

FEATURES
8- and 10-Bit Resolution
20llS Conversion Time
Microprocessor Compatibility
Very Low Power Dissipation
Parallel and Serial Outputs
Ratiometric Operation
TTL/DTL/CMOS Logic Compatibility
CMOS Monolithic Construction

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8
GENERAL DESCRIPTION

OLE
The AD7570 is a monolithic CMOS 10-bit successive approxi-
FUNCTIONAL DIAGRAM

TE
mation AID converter on a 120 by 13 5 mil chip, requiring OUT1 OUT2
only an external comparator, reference and passive clocking
components. Ratiometric operation is inherent, since an ex-
I
8 tremely accurate multiplying DAC is used in the feedback loop.
The AD7570 parallel output data lines and Busy line utilize
AIN

VREF
I
10
three-state logic to permit bussing with other AID output and ,..,....--0 DB9 (MSB)
DB8
control lines or with other I/O interface circuitry. Two enables
18
are available: one controls the two MSBs; the second controls DB1
the remaining 8 LSBs. This feature provides the control interface 19
DBO (lSBI
for most microprocessors which can accept only an 8-bit byte. 28
BUSY
The AD7570 also provides a serial data output line to be used 8
SRO
in conjunction with the serial synchronization line. The clock CaMP 27
can be driven externally or, with the addition of a resistor and BSEN

8 a capacitor, can run internally as high as 0.6MHz allowing a

total conversion time (8 bits) of typically 201ls. An 8-bit short
STRT

ClK
SUCCESSIVE
APPROXIMATION
lOGIC
20

21
HBEN

lBEN
cycle control pin stops the clock after exercising 8 bits, nor- 9
- SYNC
mally used for the "J" version (8-bit resolution).
The AD7570 requires two power supplies, a +15V main supply L-221-13l-1l-6T- -l
and a +5V (for TTL/DTL logic) to + 15V (for CMOS logic) 220 236 16 66
Vcc DGND voo AGND
supply for digital circuitry. Both analog and digital grounds
are available.

The AD7570 is a monolithic device using a proprietary CMOS

process featuring a double layer metal interconnect, on-chip
thin-film resistor network and silicon nitride passivation
ensuring high reliability and excellent long term stability.

8
Information furnished by Analog Devices is believed to be accurate
and reliable. However, no responsibility is assumed by Analog Devices P.O. Box 280; Norwood, Massachusetts 02062 U.S.
for its use; nor for any infringementS of patents or other rights of third
parties which may result from its use. No license is granted by implica- Tel:617/329-4700 Twx: 710/394-65'
tion or otherwise under any patent or patent rights of Analog Devices. Telex: 924491 Cables: ANALOG NORWOODMA:

--
SPECIFICATIONS
(VOO 0=+15V, VCC 0=+5V, VREF0=:!:lOV unless otherwise noted)
OVER SPECIFIED
PARAMETERI VERSIONS TEMP. RANGE TEST CONDITIONS
TA = +25°C ' '-- -
ACCURACY
Resolution J
L
8 Bits min
10 Bits min
8 Bits min
10 Bits min
SC8 = Logic "0"
SC8 = Logic "I"
8
Relative Accuracy J, L :!:1/2LSB max :!:1/2LSB max fCLK = 100kHz
Differential Nonlinearity 1.L ILSB max ILSB max See Figure 5
Gain Error J, L 0.3% Reading typ
Gain Temperature Coefficient J, L
---------------- 5ppm Reading per 0 C typ 10ppm Reading per
--------.-.----------.------- 0 C max
ANALOG INPUTS
Analog Input Resistance J, L 10kQ typ 5kQ Olin, 20kQ max
Analog Input Resistance Tempco 1. L -150ppm/C typ
Reference Input Resistance J, L 10kQ typ 5kQ min, 20kQ max
Reference Input Resistance Tempco J, L -I 5.9"p_n1/C- ty I' ---------------
ANALOG OUTPUTS
Output Leakage Current
(OUT!, OUT2) J, L lUnA typ 200nA max Voun, 2 = OV
Output Capacitance OUTI J, L 120pF typ DBOthrough DB9 = Logic "I"
OUT2 1.L 40pF typ
OUT!

OBS
1.L 40pF typ DBO through DB9 = Logic "0"
OUT2 J, L 120pF typ ----------.-

DIGITAL INPUTS
1.L +0_8V max
VINL 2
VINH2
VINL2
J, L
J, L
+1.4V
+2.4V
+1.5V
typ, +0.8V max
min, + 1.4V typ
max
+2.4V Olin
+ 1.5V max
Vcc = +5V

Vcc = +15V
I

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VINH2 J, L +13-5V min + 13.5V min
IINL' IINH 3 J, L :!:O_IIlA typ, :!:IOIlA max VIN = 0 to VCC
CLK Input Current J, L +0.4011\ typ, +lmA max During Conversion Vcc = +5V;
2_4V « VIN « Vcc
CLK Input Current J, L +1.7m1\ typ, +3mA max During Conversion VCC = +15V;
10V « VIN « VCC

TE
CLK Input Current 1.L :!:IIlA typ Vcc = +5V to +15V
Conversion Complete or CLK IN
« VINL
Cm J, L 2pF typ

DIGITAL
VOUTL
OUTPUTS
u ---.

J, L +0.5V max +0_8V max Vcc = +5V, ISINK = 1.6mA

I
YOUTH 1.L +2.4V min +2.4V min VCC = +5V, IsOURCE = 40llA
VOUTL 1.L +1.5V max +1.5V max VCC = +15V, ISINK = 3mA
YOUTH J, L +13.5V min +13.5V min VCC = +15V, ISOURCE = ImA
CoUT (Floating) - J, L 5pF typ VCC = +5V to +15V
(SYNC, SRO, BUSY, and SRO and SYNC; Conversion
DBO thro~gh DB9) Complete
BUSY; BSEN = Logic "0"
DBO-DB9; HBEN, LBEN =
Logic "0"
ILKG (Floating)
(SYNC, SRO, BUSY and
DBO through DB9)
:!:5nA typ VCC = +5V to +15V
SRO and SYNC; Conversion
Complete
BUSY; BSEN = Logic "0"
t
DBO-DB9; HBEN, LBEN =
Logic "0"
VOUT = OV and VCC
DYNAMIC PERFORMANCE
Conversion Time J 20lls typ, 40lls max 40lls max See Figure 5
L 40lls typ, 120lls max 120llS max
Internal CLK Frequency J, L 100kHz typ Vcc = +5V; CLK Duty Cycle =
(See Figure 2, and Section 6 50%, R = 33k, C = 760pF
of Pin Function Description) 1.L 100kHz typ VCC = +15V, CLK Duty Cycle =
50%, R = lOk; C = 2500pF
LBEN, HBEN Propagation Delay Vcc = +5V
tON J, L 650ns typ LBEN, HBEN = OV to +3V
IoFF 1.L 200ns typ Data Bit Load = 5k, 16pF
Measured from 50% of Enable
Input to 50% Point of Data
Bit Output
BSEN Propagation Delay

,
Vcc = +5V
tON J, L 450ns typ BSEN = OV to +3V
tOFF 1.L 200ns ryp BUSY Load = 5k, 16pF
Measured from 50% Point of
BSEN Input Waveform to 50% '
Point of BUSY Output Waveform -~
Convert Start (STRT)4
J, L 0.51ls Olin
Pulse Duration Requirement .--
~
"
W
-2-
i
-

--
 ----------
OVER SPECIFIED
PARAMETER VERSIONS TEMP_RANGE TEST CONDITIONS
8
I TA ~ +25°C
- ------
POWER SUPPLIES
VDD J. L +5V to +15V typ See Figures 3 and 4
VCC J. L +5V to VDD typ
IDD J. L 0.2mA typo 2mA max VDD ~ +15V, fCLK ~ 0 to 100kHz
Continuous Conversion (80% Duty
Cycle)
Icc J. L 0.02mA typ, 2mA max VCC ~ +5V. fcLK ~ 0 to 100kHz
Continuous Conversion (80% Duty
Cycle)
J, L O_lmA typ, 2mA max VCC = +15V, fcLK = 0 to 100kHz
Continuous Conversion (80% Duty
Cycle)

, "J" version parameters specified for SC8 ~ O.

2 VJNL and VJNH specifications applicable to all digital inputs except COMP. COMP terminal must be driven with CMOS levels (i.e., comparator
output pullup must be tied to VCc).
'IJNL,IJNH specifications not applicable to CLK terminal. See "CLK input current" in specifications table.

OBS
. STRT falling edge should not coincide with CLK in falling edge.
..
Specifications subject to change without notice.

8
ABSOLUTE

VootoGND
MAXIMUM RATINGS

OLE +17V
ORDERING INFORMATION

TE
VcctoGND +17V Temperature Range
Resolution
VcctoVOO"""""""""""""'" +OAV
---- -25°C to +85°C
VREFtoGND :t25V
AnaloglnputtoGND :t25V 8-Bit AD7570j
8 Digital Input Voltage Range. . . . . . . . . . . . . . VOO to GND la-Bit AD7570L

'oUTl,'oUTZ O.3V,VoO Suffix D: Ceramic Package

Power Dissipation (package)
upto+50°c IOOOmW
PIN CONFIGURATION
Derate above +50°C by. - . . . . . . . . . . . . . . . . . . IOmW/C
Operating Temperature. . . . . . . . . . . . . . . . -25°C to +85°C
TOP VIEW
Storage Temperature. . . . . . . . . . . . . . . . -65°C to +150°C
VDD 1. 2a rmw

8
VREF 27 BSEN

AIN 26

oun 25 STAT
CAUTION:
OUT2 24 ClK

1. Do not apply voltages higher than V cc or less than AGND 23 DGND

GND to any input/output terminal except VREF COMP 22 Vcc
or AIN.
SAD 21 lBEN
2. The digital control inputs are zener protected; however SYNC 20 HBEN
permanent damage may occur on unconnected units (MSB)DB9 10 19 DBa IlSB)
under high energy electrostatic fields. Keep unused DBa 11 18 DBI
units in conductive foam at all times.
DB7 12 17 DB2
3. Vcc should never exceed Voo by more than OAV, DB6 16 DB3
especially during power ON or OFF sequencing. DB5 DB4
15

- -3-
TYPICAL PERFORMANCE CHARACTERISTICS
1000.0 +0.25
VDD : +15V
CLK IN : 0 TO +3V (VCC : +5VI, +0.20

100,0
0 TO +15V IVcc : +15VI
CONVERSION.TO.STANDBY DUTY CYCLE:
HBEN, LBEN, BSEN, COMP, SClf. Vcc
:
80%

>-
+0.15
AD7570J
t
~ +0,10
~
~ ;::. +0.05
~'jj
0'"
z= 0
.y 10.0
0 <!~
_0 }AD7570L
~', -0.05
~
~
-0.10
1.0
is -0,15

.0.20

0.1
100 -0,25
lk 10k lOOk
5 10 11 12 13 14 15

CLOCK FREOUENCY - H,
VDD - VOL TS

OBS
Figure "

1M
IDD, Ice vs. fCLK at Different Temperatures Figure

0.35
3, Differential Nonlinearity vs. VDD

OLE
0.30

lOOk 1---,-
~ 0.25
VDD: +15V ."
Vcc
:I: TA:25C ~
" 0.20

TE
, ,
~
u
0:
0
R

~
22 0: 0.15
0:
10k ~ 24
w
z
~
C ~ AD7570
0.10

0.05
8
GENERATING INTERNAL CLK
[ II
lk
10 0.00
100 lk 10k
5 10 11 12 13 14 15

CAPACITANCE - pF
VDD - VOL TS

Figure 2. fCLK vs. Rand Cat Vce = +5V, +15V Figure 4, Gain Error vs. VDD (Normalized for VDD = 15V)

TEST CIRCUITS

0 TO .10V
-10V +15V 8
+5V

SW.l 3k
--
BIT 1

I (MSBI ~3
I BIT 10 LBENI 21
12 BIT

-
HBEN
BIT 11 DAC 20
BSEN
27
BIT 12
1M 250k 10.BIT, DUT 23
(LSBI TEST
sc8126 AD7570
10 BIT 8 BIT 7
TEST TEST
rv 8B'J1, 161 DB3
ANALOG DITHER INPUT TESV
5-40 H, SINE WAVE.
lOV P1'
18
100kH, CLOCK ..9:.!i 24 D80 (LSB)
19
CONVERT START STRT 10 BIT TEST
25 28 I BUSY

0.5", PULSE DN 130", INTERVALS. TRAILING OSCILLOSCOPE

e
EDGE SYNCED TO CLOCK LEADING EDGEI
20k
01

HORIZONTAL
(X) INPUT 6 VERTICAL
(YI INPUT
10k
02

DUAL "D"
NOTE, ADJUST COMPARATOR IAD311 I OFFSET TO LESS THAN O1mV. TYPE LATCH

Figure 5. Dynamic Crossplot Accuracy Test

-4-
III
 PIN FUNCTION DESCRIPTION 8. Vcc (pin 22)
8 INPUT CONTROLS
Vcc is the logic power supply. If +5V is used, all control
inputs/outputs (with the exception of comparator terminal)
1. Convert Start (pin 25 - STRT) are DTL/TTL compatible. If +15V is applied, control
When the start inpu t goes to Logical" 1 ", the MS B data inputs/outputs are CMOS compatible.
latch is set to Logic "1" and all other data latches are set to
Logic "0". When the start input returns low, the conversion OUTPUT FUNCTIONS
sequence begins. The start command must remain high for
at least 500 nanoseconds. If a start command is reinitiated 1. Busy (pin 28 - BUSY)
during conversion, the conversion sequence starts over. The Busy line indicates whether conversion is complete or
in process. Busy is a three-state output and floats until the
2. High Byte Enable (pin 20 - HBEN)
This is a three-state enable for the bit 9 (MSB) and bit 8. Busy-Enable line is addressed with a Logic "1 ". When
addressed, Busy will indicate either a "1" (conversion com-
When the control is low, the output data lines for bits
plete) or a "0" (conversion in process).
9 and 8 are floating. When the control is high, digital
data from the latches appears on the data lines. 2. Serial Output (pin 8 - SRO)

OBS
Provides output data in serial format. Data is available only
3. Low Byte Enable (pin 21 - LBEN)
during conversion. When the A/D is not converting, the
Same as High Byte Enable pin, but controls bits 0 (LSB)
Serial Output line "floats." The Serial Sync (see next func-
through 7.
~ 8 4. Busy Enable (pin 27 - BSEN)
tion) must be used, along with the Serial Output terminal
to avoid misinterpreting data.

OLE
This is an interrogation input which requests the status of
3. Serial Synchronization (pin 9 - SYNC)
the converter, i.e., conversion in process or convert com-
Provides 10 positive edges, which are synchronized to the
plete. The converter status is addressed by applying a Logic
Serial Output pin. Serial Sync is floating if conversion is
"1" to the Busy Enable. (See Busy under Output Functions.)
not taking place.
5. Short Cycle 8 Bits (pin 26 - SCS)

TE
Note that all digital inputs/outputs are TTL/DTL compatible
With a Logic "0" input, the conversion stops after 8 bits
reducing the conversion time by 2 clock periods. This when Vcc is +5V, and CMOS compatible when VCC is +15V.
control should be exercised for proper operation of the "J"

<8 version. When a Logic "1" is applied, a complete 10-bit con-

version takes place ("L" version).
PIN
6. Clock (pin 24 - CLK) NO. MNEMONIC FUNCTION
With an external RC connected, as shown in the figure
1 VDD Positive Supply (+ 15V)
below, clock activity begins upon receipt of a Convert-Start
2 VREF Voltage REFerence (:t10V)
command to the A/D and ceases upon completion of con-
3 AIN Analog INput
version. An external clock (CMOS or TTL/DTL levels) can
4 oun DAC Current OUTput 1
directly drive the clock terminals, if required. Figure 2 5 OUT2 DAC Current OUTput 2
shows the internal CLK frequency versus Rand C. If V cc 6 AGND Analog GrouND
is <4.75V, the internal CLK will not operate. 7 COMP COMParator
~ 8 8
9
SRO
SYNC
SeRial Output
Serial SYNChronization
10 DB9 Data Bit 9 (MSB)
11 DB8 Data Bit 8
+5V
12 DB7 Data Bit 7
(
13 DB6 Data Bit 6
14 DB5 Data Bit 5
R
15 DB4 Data Bit 4
16 DB3 Data Bit 3
AD7570 17 DB2 Data Bit 2
24
18 DB1 Data Bit 1
19 DBO Data Bit 0 (LSB)
CI 20 HBEN High Byte ENable
21 LBEN Low Byte ENable
22 Logic Supply (+ 5V to + 15V)
VCC
Generating Internal Clock Frequency 23 DGND Digital GrouND
24 CLK CLocK
25 STRT STaRT
~ 8 7. VDD (pin 1)
26
27
SC8
BSEN
Short Cycle 8 Bits
BuSy ENable
VDD is the positive supply for all analog circuitry plus some 28 BUSY BUSY
digital logic circuits that are not part of the TTL compatible
input/output lines (back-gates to the P-channel devices).
Nominal supply voltage is +15V. Table 1. Function Table

-5-
FUNCTIONAL ANALYSIS

BASIC DESCRIPTION
(STRT) goes HIGH, the MSB(DB9) is set to the Logic "1"
The AD7570 is a monolithic CMOS AID converter which uses state, while DBO through DB8 are reset to the "0" state.
the successive approximations technique to provide up to 10
bits of digital data in a serial and parallel format. Most AID
Two clock pulses plus 200ns after STRT retUrns LOW, the
MSB decision is made, and DB8 is tried. Each succeeding trial
t
applications require the addition of only a comparator and a and decision is made at tCLK + 200ns.
voltage or current reference.
Serial NRZ data is available during conversion at the SRO
In the successive approximations technique, successive bits,
terminal. SYNC provides 10 positive edges which occur in the
starting with the most significant bit (DB9) are applied to the
middle of each serial output bit. SYNC out must be used in
input of the 01 A converter. The DAC output is then com-
conjunction with SRO to avoid misinterpretation of data.
pared to the unknown analog input voltage (AIN) using a zero Both SYNC and SRO "float" when conversion is not taking
crossing detector (comparator). If the DAC output is greater
place.
than AIN, the data latch for the trial bit is reset to zero, and
the next smaller data bit is tried. If the DAC output is less
than AIN, the trial data bit stays in the "1" state, and the next 8-BIT SHORT CYCLE NOTES
smaller data bit is tried.
If the AD7570 is short cycled to 8 bits (SC8 = OV), the

OBS
Each successive bit is tried, compared to AIN, and set or reset following will occur:
in this manner until the least significant bit (DBO) decision is
1. The SYNC terminal will provide 8, instead of 10, positive
made. At this time, the AD7570 output is a valid digital rep-
output pulses.
resentation of the analog input, and will remain in the data
latches until another convert start (STRT) is applied. 2. OBI goes "high" coincident with the LSB (DB2 is the LSB
when short cycled to 8 bits) decision, and remains high t

OLE
until another STRT is initiated. DBO remains in the "0"
TIMING DESCRIPTION state.

Figure 6 is the AD7570 timing diagram, showing the successive 3. BUSY goes "high" one clock period after the DB2 (DB2 is
trials and decisions for each data bit. When convert start the LSB when short cycled) decision is made.

ClK1
STRT2
SYNC3, 4,8
SROS,8

OB9 (MSB)6,7
0B87
:///////1
////////1T
II

, IMSBI8 17 f6l
TRYMSB1-- MSBDECISION
RY'DBB-! E DB8DECISION
5 14 13 1211
TE
---------
!LSBr---------
t

OB77 ////////1 TRYDB7--/ I~ DB7 DECISION

OB67 ////////1 TRY DB6==:/ E DB6 DECISION

OB57 ///////~ TRY DB5 ~ E DBS DECISION t
0B47 ////////1 TRY DB4 d E DB4 DECISION

OB37 :///////~ TRY DB3 ~ E DB3 DECISION

OB27 ////////1 TRY DB2==:1 EDB2 DECISION

OB17 ////////1 TRY DB1 ==:/ E DB1 DECISION

DBa (lSB)7 all////~ TRY LSB ==:/ E DBO (LSBI DECISION

BSEN2
BUSY -- , BUSY
JCOMPLETE
CONVERT L..- - - -
NOTES:
1. INTERNAL CLOCK RUNS ONLY DURING CONVERSION CYCLE (EXTERNAL CLOCK SHOWN!.
2. EXTERNALLY INITIATED.
3. SERIAL SYNC LAGS CLOCK BY '" 200ns.
4. DOTTED LINES INDICATE "FLOATING" STATE.
5. FOR ILLUSTRATIVEPURPOSES,SERIAL OUTSHOWNAS 1101001110.
6. CROSS HATCHING INDICATES "DON'T CARE" STATE. 411
7. SET AND RESET OF OUTPUT DATA BITS LAGS CLOCK POSITIVE EDGE BY '" 200ns.
8. SHOWN FOR sca = 1.

Figure 6. AD7570 Conversion Timing Sequence

-6-

--
 DYNAMIC PERFORMANCE Worst case settling requirements occur when a trial bit causes
~ (8 The upper clock frequency limitation (hence the conversion
speed limitation) of the AD7570 is due to the output settling
the OUTI terminal to charge towards a final value which is
precisely 1/2 LSB beyond zero crossing. When this occurs,
the trial bit must settle and remain within 1/2 LSB of final
characteristics of the current weighting DAC in conjunction
with the propagation delay of the comparator, not to speed val ue, or an incorrect decision will be made by the comparator.
limitations in the digital logic. For 10-bit accuracy, the first MSB must settle to within 0.1 %
of final value; the second MSB to within 0.2%. The LSB
DAC EQUIVALENT CIRCUIT settling requirement is only 50% of the LSB value. Figure 8
The Df A converter section of the AD75 70 is a precision lO-bit illustrates the settling time available during a given clock
period. The pulse shown on the OUTI terminal falling mid-
multiplying DAc. The simplified DAC circuit, shown in Figure
way between to and q is a feed through from internal clock
7, consists of ten single-pole-double-throw current steering
switches and an "inverted" R-2R current weighting network. mechanisms and is due primarily to bonding wire and header
capacitance. Two methods may be used to reduce the OUTI
(For a complete description of the DAC, refer to the AD7520
data sheet.) settling time:

1. Load OUTI with a lk resistor. This reduces the time

OBS
The output resistance and capacitance at OUTI (and OUT2)
J are code dependent, exhibiting resistive variations from 0.5 constant by a factor of 10. Further reduction of the lkD.
"R" to 0.75 uR", and capacitive variations from 40pF to load reduces the amount of comparator overdrive, thus in-
l20pF. creasing the comparator propagation delay, resulting in a
. , (8 reduction of available settling time (tl - to on Figure 8).

OLE
10k 10k 10k 2. Use a zero input impedance comparator. Figure 9 illustrates
VREF
a comparator circuit which has an input impedance of
2Ok 20k 20k 20k 20k approximately 26D.. Proper circuit layout will provide
lO-bit accuracy for clock frequencies >500kHz.
A / ANALOG
GNo

TE
OUT2 ClK IN 1
oun
I I I

. 8 I
oB9
I
oB8
I
oB7
AIN COMPARATOR
INPUT
louni

Figure 7. DAC Circuit

NOTES'
SETTLING TIME ANALYSIS 1 "',mUNG" "1 . '01 IS THE TIME REOUIRED FOR THE oun TERMINAL TO
SETTLE WITHIN .1/2LS6 OF THE FINAL VALUE.
2. "'COM'" 11, . 1, I IS THE COMPARATOR SWITCHING TIME
Due to the changing COUTI and ROUTl, the time constant 3 "'O'lAY" 11, - 1,IIS AN INTERNAllY GENERATED TIME DELAY EOUAL TO
APPROXIMATEL Y 400 NANOSECONDS.
on OUTI falls anywhere between 250 and 900ns, depending 4 COMPARATOR OUTPUT IS LATCHES AT TIME "

on the instantaneous state of the AD7570 digital output code.

Figure 8. Expanded Timing Diagram

- 8 +5V Vcc

R1 R2 R6
1k 1k
0.01% 0.01% 1k

OUT1
R4
AD7570 I 7.5k R5 7.5k
0.05% 100 0.05%
OUT2 R3U
. (8 CaMP \AI !
-15V

Figure 9. Current Comparator With Low Input Impedance

-7-
OPERATION GUIDELINES
UNIPOLAR BINARY OPERATION ADJUSTMENT PROCEDURES UNIPOLAR OPERATION

Figure 10 shows the circuit connections required for unipolar

analog inputs. If positive analog inputs are to be quantized,
VREF must be negative, and the OUT1 (pin 4) terminal of the
Gain Adjustment
1. Apply continuous
AD7570.
start commands to the STRT input of the t
AD7570 must be connected to the "+" comparator input. For
2. Apply full scale minus 1-1/2LSB to AIN.
negative analog inputs, VREF must be positive, and the OUT1
terminal connected to the "-" input of the comparator. 3. Observe the S RO terminal as described under zero offset
procedure above, and adjust the gain potentiometer (R4)
For clarity, the digital control functions have been omitted until the LSB flickers between 0 and I, and all other data
from the diagram. For proper use of the digital input/output
control functions, refer to the pin function description. bits equal "I". An alternate method is to adjust VREF
instead of using R4.

The input voltage/output code relationship for unipolar vcc

+5V TO +15V
operation is shown in Table 2. Due to the inherent multiplying VDD
+15V
capability of the internal D/A converter, the AD7570 can ac-
+15V
curately quantize full scale ranges of 10V to 1V. It should be R2
22 3k
noted, however, that for smaller full scale ranges, the resolu-

OBS
4 I oun
tion and speed limitations of the comparator impose a VREF. 2
~fJv R3
limitation on the maximum conversion rate.
20011 AD7570

BIPOLAR (OFFSET BINARY) OPERATION

~N:ci"~~o~N ~ R4
3
t

OLE
Figure 11 shows the AD7570 configured for offset binary
(modified 2's complement) operation. Input voltage/output
GAI~kADJ I 23

codes are shown in Table 3.

Amplifier AI, in conjunction with resistors R1, R2, and R3,

0ffsets the bipolar analog input by full scale, and reduces its

TE
NOTE:
gain by a factor of 2. The analog signal applied to the AIN IF POSITIVE VREF IS USED. THE ANALOG INPUT RANGE IS 0 TO -VREF. AND THE
COMPARATOR'S (-) INPUT SHOULD BE CONNECTED TO oun (PIN 4) OF THE
terminal is, therefore, a unipolar signal of 0 to +V or 0 to -V, AD7570.
depending on the polarity of VREF'
Figure 10. Unipolar Operation t
VREF VDD Vcc
-10V +15V +5V TO +15V

+15V
R2 R6
20k 3k
2
t
R5
R3 R5 VREFI 4 rUTl1k
2 22
20k 10k 200 3
5 OUT2'
R1
AD7570
BIPOLAR
ANALOG AGND
INPUT
+10V TO -10V 3

7
COMP

NOTE: IF POSITIVE VREF IS USED, CONNECT MINUS INPUT OF COMPARATOR

TO oun (PIN 4) OF THE AD7570.

Figure 11. Bipolar Operation

I

-8-
 Table 2. Unipolar Operation Table 3. Bipolar Operation
(8
Analog Input Digital Output Code Analog Input Digital Output Code
(AIN) (AIN)
Notes 1, 2, 3 MSB LSB Notes 1, 2, 3 MSB LSB

FS - lLSB 1111111111 +(FS - 1LSB) 1111111111

FS - 2LSB 1111111110 +(FS - 2LSB) 1111111110
3/4 FS 1100000000 +(1/2 FS) 1100000000
1/2 FS + lLSB 1000000001 +(1LSB) 1000000001
1/2 FS 1000000000 0 1000000000
1/2 FS - lLSB 01111 11 111 -(1LSB) 0111111111
1/4 FS 0100000000 -(1/2 FS) 0100000000
lLSB 0000000001

OBS
0000000001 -(FS - lLSB)
0 0000000000 -FS 0000000000

NOTES: NOTES:
(8 1. Analog inputs shown are nominal center values 1. Analog inputs shown are nominal center values

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of code. of code.
2. "FS" is full scale, i.e., (-VREF)' 2. "FS" is full scale; i.e., (VREF)'
3. For 8-bit operation, lLSB equals (-VREF) 3. For 8-bit operation, lLSB equals (-VREF)
(Z-8); for to-bit operation, lLSB equals (Z-7); for to-bit operation, lLSB equals
(-VREF) (2-10). (-VREF) (2-9).

(8 ADJUSTMENT

Gain Adjustment
1. Apply continuous
the AD7570.
PROCEDURES

start commands
BIPOLAR OPERATION

to the STRT input of

2. Apply 1-1/2LSB less than positive full scale (FS = VREF)

TE
6. If an external clock is used, the negative transition of STRT
should not coincide with the trailing edge of the clock
input.

OPERA TING PRECAUTIONS

to the bipolar analog input of Figure 11.
1. Do not allow Vcc to exceed VDD' In cases where Vcc
could exceed VDD' the diode protection scheme in Figure
3. Trim the gain potentiometer R4 for a flickering LSB, and 12 is recommended.
(8 all other data bits equal to Logic "1". Observe the SRO
terminal, as described in zero offset procedure above. 2. Do not apply voltages greater than V cc or lower than
ground to any digital output from sources which can sup-
ply >20mA.
APPLICATION HINTS
3. Do not apply voltages (from a source which can supply
more than SmA) lower than ground to the OUTI or OUT2
1. Unused CMOS digital inputs should be tied to their appro- terminal (see Figure 12).
priate logic level and not left floating. Open digital inputs
may cause undesired digital activity in the presence of noise. Voo
Vcc
2. Analog and digital grounds should have separate retUrns.
1N459,
1N914
3. Load the OUTI terminal with a 1k resistor to reduce the
HP5082-2811
time constant when operating at clock frequencies
>50kHz.
22
4 .OUT1
4. For 10-bit operation, the comparator offset should be
adjusted to less than ImV. Each millivolt of comparator AD7570
(8 offset will cause approximately 0.015% of differential
nonlinearity when a 10V reference is used.

5. The comparator input and output should be isolated to

prevent oscillations due to stray capacitance. (See layout
on the next page). Figure 12. Diode Protection Scheme

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APPLICA nONS
OPTIMIZED LAYOUT

~
~
'j i ~ ..
t
AD7570-t

oun
Ik LOAD

OBS NOTES:
1. ALL PC TRACES ON BOTTOM OF BOARD.
- ~

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2. LAYOUT SHOWN TERMINATES oun INTO + INPUT OF AD311 TYPE COMPARATOR.
IVREF . -JOY. AIN' 0 TO +IOV).

Figure 13. PC Layout (Top View)

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BUSING MULTIPLE AD7570 OUTPUTS

Several AD7570's may be paralleled to a data bus to provide available at the AID output only after conversion is complete,
an AID converter per analog channel, this providing increased
system throughput rate. For example, Figure 14 shows such
and until another "convert start" is initiated. The timing
diagram of Figure 15 illustrates how the STRT signals of the
t
a system for 12 AD7570's in parallel. twelve AD7570's might be staggered to provide a total system
throughput twelve times as great as the classic method of data
The three-state output logic enables of each AD7570 is con- acquisition (an analog multiplexer feeding multichannel analog
trolled by its own BUSY (status) outputs. Thus, data is data to a single AID converter).

STRT 1

BSEN1

AIN 1
OB9 (MSB)
.
I
I
t
A07570 lOBO (LSB) I
NO.1
LBEN
I
BUSY 1
CLK 0 --, I CLK
I/O
DATA
BUSS.
STRn CD -11
REA01
,OB9,OB8,OB7,OB6,OB5,084,OB3,OB2,081,OBO,
READ1
L-
VREF
STRT12
BUSY 1 ~ CONVERSION IN PROCESS ~
BSEN 12
OB9 (MSB)
I
STRn
CD
~ ---1L
. REA02 READ 2
AIN 12
I
I BUSY2 ~ CONVERSION IN PROCESS ~
LBEN
A07570
NO. 12
lOBO (LSB) I
STRT 12
CD
n
READ 12
I
BUSY 3
BUSY 12 CONVERSION IN PROCESS
~
NOTE: STRT SIGNAL 0.5!,s PULSE WIDTH, LEADING
EDGE SYNCHRONIZED TO CLK TRAILING EDGE.

8
NOTE: BSEN ON EACH A07570 IS "ENABLEO" (LOGIC 1).

Figure 14. Busing Multiple AD7570's Figure 15. Timing Diagram

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 MICROPROCESSOR INTERFACE

8 Since most 8-bitmicroprocessors utilize a bidirectio~al data

bus, each input peripheral (such as the AD7570) must be
3. LBEN is enabled, and the eight least significant data bits
(DBO-DB7) are applied to the data bus for subsequent trans-
capable of isolating itself from the data bus when other I/O fer to the 8080. When the data transfer is complete, LBEN
devices, memory, or the CPU takes control of the bus. The is disabled, and DBO-DB7 return to their floating state.
AD7570 output data and status (BUSY) lines all utilize three- 4. HBEN is enabled, and the two most significant AD7570 data
state logic to provide this requirement. bits (DB8 and DB9) are applied to the data bus for subse-
quent transfer to the 8080. When the data transfer is
Figure 16 illustrates a method of interfacing a TTY keyboard
complete, HBEN is disabled, and DB8 and DB9 return to
and printer to the AD7570, using an 8080 microprocessor as
the interface controller. their floating state.

The program (stored in Read Only Memory) waits for a key- 5. The 8080 (in conjunction with the programmed Read Only
stroke on the TTY keyboard. When a keystroke is detected, Memory) performs a binary to decimal conversion.
an AID conversion is started. When conversion is complete,
the 8080 reads in the binary data from the AD7570, converts 6. SWE (Status Word Enable) on the UAR/T transmitter is

OBS
it to ASCII, and prints out the decimal number (preceded by a enabled, applying XBMT (Transmitter Buffer Empty) to
carriage return and line feed) on the teletype printer. the data bus. When a Logic "1" is detected by the 8080,
SWEis disabled, and XBMT returns to a floating state.
More specifically, the main sequence of events would be as
~ 8 follows: 7. TDS (Transmitter Data Strobe) strobes the converted

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1. When a TTY keystroke is detected by the CPU (via the decimal number into the UAR/T transmitter for subsequent
UAR/T Receiver), a "convert start" (STRT) is applied to serial clocking into the keyboard.
the AD7570.

2. BSEN is enabled, placing BUSY (conversion status) on the The interface scheme shown below is only one example of a
data bus. When the 8080 detects BUSY = 1, conversion is myriad of possible data acquisition/control systems which

TE
complete, and BSEN is disabled, causing BUSY to return to could conveniently use the AD7570 to provide digital data to
its floating state. a microprocessor or minicomputer bus.

~ 8
A15

A8
DBFLlN . MEMR . A2
A7 I
ADDRESS BUSS DBFLlN . MEMR . A4
AO DBFLlN

BSEN HBEN

~ 8 (MSBI
BOSY DB9 8 7
AD7570 ADC

6 5 4 3 2 1
(lSB)
BDO
-, ,
DBFLlN . MEMR
8080

DATA BUSS
DO-D7 DO D1 DO D7 D6 03 D2 D1 DO
DO DO D7 Dol 07'

RDA XBMT
MEMR
FROM RSI D Q
UAR/T REC UAR/T XMT
KEYBOARD
RDAR RDE SWE TDS
WR

DBFLlN ClK O.MEMR

WR A2
SYNC WR . AO TO PRINTER
:J1 . SYNC
. 8 DBFLlN . MEMR . AT
DBFLlN . MEMR . AO

Figure 16. Microprocessor Controlled TTY IADC Interface

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..
TERMINOLOGY
Resolution Differential Nonlinearity
Resolution is the relative value of the LSB, or Z-n for binary In a converter, differential linearity error describes the variation
devices, for n-bit converters. It may be expressed as 1 part in in the analog value of transitions between adjacent pairs of
Zn, as a percentage, in parts-per-million, or simply by "n bits." digital numbers, over the full range of the digital input or 4
output. If each transition is equal to its neighbors (i.e., 1LSB),
Relative Accuracy the differential nonlinearity is zero. If a transition differs
Relative accuracy error is the difference between the nominal from one of its neighbors by more than 1LSB (e.g., if, at the
and actUal ratios to full scale of the analog value corresponding transition OIl. .11 to 100. . .00, the MSB is low by 1.1LSB),
to a given digital input, independently of the full-scale calibra- a DI A converter can be non-monotonic, or an AID converter
tion. This error is a function of the linearity of the converter, using it may miss one or more codes. A sp,ecified maximum
and is usually specified at less than :!:l/2LSB. differential nonlinearity of 1 LSB ensures that monotonic
behavior exists.
Gain Error
The "gain" of a converter is that analog scale factor setting Output Leakage Current
that establishes the nominal conversion relationship, e.g., lOV Current which appears at the OUT1 terminal when all digital
full scale. It is adjusted either by setting the feedback resistor output (DBO through DB9) are LOW, or on the OUTZ terminal
of a DAC, the input resistor in a current-comparing ADC, or when all digital outputs are HIGH. The effect of output leakage

OBS
the reference (voltage or current). current will be on the offset of the AID converter.

OUTLINE DIMENSIONS 4

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Dimensions shown in inches and (mm).

[2.j~1

L
r
M.AX
~~~~~c=J~~~~li~
.
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0.065
0.045
"

[1.661
[1151

LEADS
1414[35921
138 135061'

--11--
0.02
0015
.

10.5081
[0381}
--1
0105
0.095
f--
[2671
12.42}
~.--
~
~
0125
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LEAD NO 1 IDENTIFIED BY DOT OR NOTCH

ARE GOLD PLATED [50 MICROINCHES MIN[ KOVAR
t
1318}
,

I 0.606
1--~--1
[1541

OR ALLOY 42
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1
[1531

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:::::::::
4

28 Pin Ceramic Dip

-12-