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Ecen 248 Prelab 10

This document describes Verilog code for implementing a carry lookahead adder. It includes modules for generating propagate and generate signals, calculating the carry signals, and performing the summation. The code samples show how these modules are instantiated and connected to build a 4-bit carry lookahead adder with a gate count of 26 gates and a propagation delay of 8 gates.

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Rebecca Sontheimer
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553 views2 pages

Ecen 248 Prelab 10

This document describes Verilog code for implementing a carry lookahead adder. It includes modules for generating propagate and generate signals, calculating the carry signals, and performing the summation. The code samples show how these modules are instantiated and connected to build a 4-bit carry lookahead adder with a gate count of 26 gates and a propagation delay of 8 gates.

Uploaded by

Rebecca Sontheimer
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Rebecca Sontheimer

Pre-Lab 10
1.
module generate_propagate_unit (G, P, X, Y);
output wire [15:0] G, P;
input wire [15:0] X, Y;
assign G = X & Y;
assign P = X ^ Y;
endmodule
module carry_lookahead_unit (C, G, P, C0);
output wire [4:1] C;
input wire [3:0] G, P;
input wire C0;
assign C[1] = G[0] | P[0] & C0;
assign C[2] = G[1] | P[1] & G[0] | P[1] & P[0] & C0;
assign C[3] = G[2] | P[2] & G[1] | P[2] & P[1] & G[0] | P[2] & P[1] & P[0] & C0;
assign C[4] = G[3] | P[3] & G[2] | P[3] & P[2] & G[1] | P[3] & P[2] & P[1] & G[0] |
P[3] & P[2] & P[1] & P[0] & C0;
endmodule
module summation_unit(S,P,C);
output wire [15:0] S;
input wire [15:0]P,C;
assign S=P^C;
endmodule

2.
module carry_lookahead_4bit (Cout, S, X, Y, Cin);
output wire Cout;
output wire [3:0] S;
input wire [3:0] X, Y;
input wire Cin;
wire [3:0] G, P;
wire [4:0] C;
assign C[0] = Cin;
generate_propagate_unit gp0 (G, P, X, Y);
carry_lookahead_unit cl0 (C[4:1], G, P, Cin);
summation_unit s0 (S, P, C[3:0]);
assign Cout = C[4];
endmodule
3. The gate count for the 4-bit carry-lookahead adder is 26 gates.
4. The propagation delay of the 16-bit, 2-level carry-lookahead adder is 8 gates with a
gate count of 82.

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