32-bit Superscalar RISC-V CPU

An Open-source FPGA IP Generator

Various HDL (Verilog) IP Cores

mor1kx - an OpenRISC 1000 processor IP core

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

An open source FPGA design for DSLogic

Raptor end-to-end FPGA Compiler and GUI

Multi-threaded 32-bit embedded core family.

IP Catalog for Raptor.

Yosys + (Optional) Verific Integration