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CICC 2008: San Jose, California, USA
- Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, CICC 2008, DoubleTree Hotel, San Jose, California, USA, September 21-24, 2008. IEEE 2008, ISBN 978-1-4244-2018-6
Keynote
- Dave Bergeron:
More than Moore.
Session 2 - Statistical modeling
- Hidetoshi Onodera, Hong-Ha Vuong:
Session 2 - Statistical modeling. - Sani R. Nassif:
Process variability at the 65nm node and beyond. 1-8 - Larry T. Pileggi, Gökçe Keskin, Xin Li, Ken Mai
, Jonathan E. Proesel:
Mismatch analysis and statistical design at 65 nm and below. 9-12 - Wenping Wang, Vijay Reddy, Bo Yang, Varsha Balakrishnan, Srikanth Krishnan, Yu Cao:
Statistical prediction of circuit aging under process variations. 13-16
Session 3 - Power management
- Gordon Lee, Makoto Takamiya:
Session 3 - Power management. - Mike Wens, Michiel Steyaert
A fully-integrated 0.18μm CMOS DC-DC step-down converter, using a bondwire spiral inductor. 17-20 - Pengfei Li, Deepak Bhatia, Lin Xue, Rizwan Bashirullah:
A 90-240MHz hysteretic controlled DC-DC buck converter with digital PLL frequency locking. 21-24 - Chia-Hsiang Lin, Hong-Wei Huang, Ke-Horng Chen
Fast transient technique (FTT) in buck current-mode DC-DC converters for low-voltage SoC systems. 25-28 - Fumihiko Tachibana, Hironori Sato, Takahiro Yamashita, Hiroyuki Hara, Takeshi Kitahara, Shuou Nomura, Fumiyuki Yamane, Yoshiro Tsuboi, Keiko Seki, Shuuji Matsumoto, Yoshinori Watanabe, Mototsugu Hamada:
A process variation compensation scheme using cell-based forward body-biasing circuits usable for 1.2V design. 29-32 - Chia-Hsiang Lin, Hong-Wei Huang, Ke-Horng Chen
Built-in resistance compensation (BRC) technique for fast charging Li-Ion battery charger. 33-36
Session 4 - High-speed test, characterization, and debug
- Mike Li, Gordon W. Roberts:
Session 4 - High-speed test, characterization, and debug. - Genichi Tanaka, Kan Takeuchi, Minoru Ito, Hiroaki Matsushita:
A voltage drop aware crosstalk measurement with multi-aggressors in 65nm process. 37-40 - Gerry Talbot, Edoardo Prete:
Measurements of the silicon die characteristics of packaged drivers for high-speed I/O. 41-48 - Steven Thijs, Mototsugu Okushima, Jonathan Borremans, Philippe Jansen, Dimitri Linten, Mirko Scholz, Piet Wambacq, Guido Groeseneken
Inductor-based ESD protection under CDM-like ESD stress conditions for RF applications. 49-52 - Edward I. Cole Jr.:
Non-destructive IC defect localization using optical beam-based imaging. 53-56
Session 5 - Broadband circuit techniques for emerging wireless communications
- Fa Foster Dai, Howard C. Luong:
Session 5 - Broadband circuit techniques for emerging wireless communications. - John D. Cressler:
Emerging application opportunities for SiGe technology. 57-64 - Shuzuo Lou, Howard C. Luong
A 0.8GHz-10.6GHz SDR low-noise amplifier in 0.13-μm CMOS. 65-68 - Zahra Safarian, Hossein Hashemi:
A 1.3-6 GHz triple-mode CMOS VCO using coupled inductors. 69-72
Session 6 - Advanced SoC/SiP integration & co-design
- Rich Liu, Philippe Jansen:
Session 6 - Advanced SoC/SiP integration & co-design. - Joy Laskar, Stephane Pinel, Saikat Sarkar, Padmanava Sen, Bevin G. Perunama, Debasis Dawn, David Yeh, Francesco Barale:
A SOC/SOP co-design approach for mmW CMOS in QFN technology. 73-80 - Eric D. Perfecto, Brian Sundlof, Kamalesh Srivastava, Minhua Lu:
Chip to carrier C4 technology challenges with Pb free solders. 81-84 - Kazuhiro Takahashi, Makoto Mita, Hiroyuki Fujita, Kazuhiro Suzuki, Hideyuki Funaki, Kazuhiko Itaya, Hiroshi Toshiyoshi:
A study on process-compatibility in CMOS-first MEMS-last integration. 85-88
Session 7 - High resolution converters
- Yusuf Haque, George LaRue:
Session 7 - High resolution converters. - Moo-Yeol Choi, Sung-No Lee, Seung-Bin You, Wang-Seup Yeum, Ho-Jin Park, Jae-Whui Kim, Hae-Seung Lee:
A 101-dB SNR hybrid delta-sigma audio ADC using post integration time control. 89-92 - Kyehyung Lee, Matthew R. Miller, Gabor C. Temes:
An 8.1 mW, 82 dB delta-sigma ADC with 1.9 MHz BW and -98 dB THD. 93-96 - Yan Wang, Kyehyung Lee, Gabor C. Temes:
A 2.5MHz BW and 78dB SNDR delta-sigma modulator using dynamically biased amplifiers. 97-100 - Nima Maghari, Sunwoo Kwon, Un-Ku Moon:
74dB SNDR multi-loop sturdy-MASH delta-sigma modulator using 35dB opamp gain. 101-104 - Boris Murmann
A/D converter trends: Power dissipation, scaling and digitally assisted architectures. 105-112 - Tae-Hwan Oh, Ho-Young Lee, Ju-Hwa Kim, Ho-Jin Park, Kyoung-Ho Moon, Jae-Whui Kim, Hae-Seung Lee:
A 16b 10MS/s digitally self-calibrated ADC with time constant control. 113-116 - Shoji Kawahito, Kazutaka Honda, Zheng Liu, Keita Yasutomi, Shinya Itoh:
A 15b power-efficient pipeline A/D converter using non-slewing closed-loop amplifiers. 117-120
Session 8 - Characterization and test methods for device variability in nanoscale technologies
- Hamid Mahmoodi
Session 8 - Characterization and test methods for device variability in nanoscale technologies. - John Keane, Shrinivas Venkatraman, Paulo F. Butzen
An array-based test circuit for fully automated gate dielectric breakdown characterization. 121-124 - Mesut Meterelliyoz, Peilin Song, Franco Stellari, Jaydeep P. Kulkarni, Kaushik Roy:
A high sensitivity process variation sensor utilizing sub-threshold operation. 125-128 - Liang-Teck Pang, Borivoje Nikolic
Measurement and analysis of variability in 45nm strained-Si CMOS technology. 129-132 - Bishnu Prasad Das, Bharadwaj Amrutur, H. S. Jamadagni, N. V. Arvind, V. Visvanathan:
Within-die gate delay variability measurement using re-configurable ring oscillator. 133-136 - Taro Niiyama, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai:
Expected vectorless Teacher-Student Swap (TSS) test method with dual power supply voltages for 0.3V homogeneous multi-core LSI's. 137-140
Session 9 - Broadband circuit techniques for emerging wireless communications
- Fa Foster Dai, Howard C. Luong:
Session 9 - Broadband circuit techniques for emerging wireless communications. - Yorgos Palaskas, Ashoke Ravi, Stefano Pellerano:
MIMO techniques for high data rate radio communications. 141-148 - Swaminathan Sankaran, Kyujin Oh, Hsin-Ta Wu, Kenneth K. O:
Wireless interconnection within a hybrid engine controller board. 149-152
Session 10 - Panel discussion Sure, Moore's Law can continue, but should it
- David A. Sunderland, Kazuyuki Kawauchi, John Kent, Randy Mooney, Chuck Moore, Clark T.-C. Nguyen:
Session 10 - Panel discussion Sure, Moore's Law can continue, but should it. - Jonathan E. Proesel, Lawrence T. Pileggi:
A 0.6-to-1V inverter-based 5-bit flash ADC in 90nm digital CMOS. 153-156 - Yun-Shiang Shu, Moon-Jung Kyung, Wei-Ming Lee, Bang-Sup Song, Bedabrata Pain:
A 10∼15b 60MS/s floating-point ADC with digital gain and offset calibration. 157-160 - Parastoo Nikaeen, Boris Murmann
Digital correction of dynamic track-and-hold errors providing SFDR ≫ 83 dB up to fin = 470 MHz. 161-164 - Kang-Jin Lee, Kyoung-Jun Moon, Kwang-Sung Ma, Kyoung-Ho Moon, Jae-Whui Kim:
A 65nm CMOS 1.2V 12b 30MS/s ADC with capacitive reference scaling. 165-168 - David Gubbins, Bumha Lee, Pavan Kumar Hanumolu, Un-Ku Moon:
A continuous-time input pipeline ADC. 169-172 - Michael Trakimas, Sameer R. Sonkusale:
A 0.8 V asynchronous ADC for energy constrained sensing applications. 173-176 - Xiaochun Wu, Alireza Khaligh, Yang Xu:
Modeling, design and optimization of hybrid electromagnetic and piezoelectric MEMS energy scavengers. 177-180 - Rahul Shringarpure, Lawrence T. Clark, Sameer M. Venugopal, David R. Allee, Shrinivas G. Uppili:
Amorphous silicon logic circuits on flexible substrates. 181-184 - Frederic Nabki
Frequency tunable silicon carbide resonators for MEMS above IC. 185-188 - Dominique Lemoine, Paul-Vahe Cicek, Frederic Nabki
MEMS wafer-level vacuum packaging with transverse interconnects for CMOS integration. 189-192 - Jing Li
Variation-tolerant Spin-Torque Transfer (STT) MRAM array for yield enhancement. 193-196 - Liyang Pan, Xian Luo, Yaru Yan, Jirong Ma, Dong Wu, Jun Xu:
Pure logic CMOS based embedded Non-Volatile Random Access Memory for low power RFID application. 197-200 - H. Henry Nho, Mark Horowitz, S. Simon Wong:
A high-speed, low-power 3D-SRAM architecture. 201-204 - Choongyeun Cho, Daeik D. Kim, Jonghae Kim, Daihyun Lim, Sangyeun Cho:
Early prediction of product performance and yield via technology benchmark. 205-208 - Poki Chen, Juan-Shan Lai, Po-Yu Chen:
A FPGA vernier digital-to-time converter with 3.56ps resolution and -0.23∼+0.2LSB inaccuracy. 209-212 - Arindam Basu
RASP 2.8: A new generation of floating-gate based field programmable analog array. 213-216 - Piljae Park, C. Patrick Yue
Modeling of triple-well isolation and the loading effects on circuits up to 50 GHz. 217-220 - Wei Cheng, Anne-Johan Annema
A general weak nonlinearity model for LNAs. 221-224 - Bodhisatwa Sadhu
Modeling and synthesis of wide-band switched-resonators for VCOs. 225-228 - Ben Gu, Kiran K. Gullapalli, Yun Zhang, Savithri Sundareswaran:
Faster statistical cell characterization using adjoint sensitivity analysis. 229-232 - Yuan-Wen Hsiao, Ming-Dou Ker:
An ESD-protected 5-GHz differential low-noise amplifier in a 130-nm CMOS process. 233-236 - Jongshin Shin, Jaehyun Park, Bongjin Kim, Jongjae Ryu, Chiwon Kim, Jiyoung Kim, Seung-Hee Yang, Hyungoo Kim, Jaewhui Kim:
A 65nm 3.4Gbps HDMI TX PHY with supply-regulated dual-tuning PLL and blending multiplexer. 237-240 - Hungwen Lu, Chauchin Su, Chien-Nan Liu:
A scalable digitalized buffer for gigabit I/O. 241-244 - Ji-Chen Huang, Yu-Sheng Lai, K. Hsu:
Broadband transimpedance amplifier in 0.35-μm SiGe BiCMOS technology for 10-Gb/s optical receiver analog front-end application. 245-248 - Yin Shi, Foster F. Dai, Jun Yan, Xueqing Hu, Hua Xu, Ming Gu, Xuelian Zhang, Qiming Xu, Bei Chen, Fangxiong Chen, Peng Yu, Heping Ma, Fang Yuan, Richard C. Jaeger:
A multifunction transceiver RFIC for 802.11a/b/g WLAN and DVB-H applications. 249-252 - Yin Shi, Fa Foster Dai, Jun Yan, Hua Xu, Xuelian Zhang, Heping Ma, Fang Yuan, Xin Guan, Richard C. Jaeger:
A fully integrated zero-IF mobile TV tuner RFIC for S-band CMMB application. 253-256
Session 11 - Compact modeling
- Gennady Gildenblat, Brian Chen:
Session 11 - Compact modeling. - Yuan Taur, Jooyoung Song, Bo Yu:
Compact modeling of multiple-gate MOSFETs. 257-264 - Jung-Suk Goo, Richard Q. Williams, Glenn O. Workman, Qiang Chen, Sungjae Lee, Edward J. Nowak:
Compact modeling and simulation of PD-SOI MOSFETs: Current status and challenges. 265-272 - Hugh J. Barnaby, Michael L. McLain, Ivan Sanchez Esqueda, Xiao J. Chen:
Modeling ionizing radiation effects in solid state materials and CMOS devices. 273-280 - Ning Lu, Bill Dewey:
Characterization, simulation, and modeling of FET source/drain diffusion resistance. 281-284 - Minki Cho, Kingsuk Maitra, Saibal Mukhopadhyay:
Analysis of the impact of interfacial oxide thickness variation on metal-gate high-K circuits. 285-288 - David G. Nairn:
Time-interleaved analog-to-digital converters. 289-296 - Hao Yu, Sing W. Chin, Bill C. Wong:
A 12b 50MSPS 34mW pipelined ADC. 297-300 - Cheongyuen W. Tsang, Yun Chiu, Johan P. Vanderhaegen, Sebastian Hoyos, Charles Chen, Robert W. Brodersen, Borivoje Nikolic
Background ADC calibration in digital domain. 301-304 - Pratap Narayan Singh, Ashish Kumar, Chandrajit Debnath, Rakesh Malik:
A 1.2v 11b 100Msps 15mW ADC realized using 2.5b pipelined stage followed by time interleaved SAR in 65nm digital CMOS process. 305-308 - Zhiheng Cao, Shouli Yan:
A 52mW 10b 210MS/s two-step ADC for digital-IF receivers in 0.13μm CMOS. 309-312 - Jaesik Lee, Joseph Weiner, Pascal Roux, Andreas Leven, Young-Kai Chen:
A 24GS/s 5-b ADC with closed-loop THA in 0.18μm SiGe BiCMOS. 313-316
Session 13 - Biomedical, sensors and MEMS
- Makoto Nagata
Session 13 - Biomedical, sensors and MEMS. - Eusebiu Matei, Edward K. Lee, John Gord, Patrick Nercessian, Phil Hess, Howard Stover, Taihu Li, James Wolfe:
A biomedical implantable FES battery-powered micro-stimulator. 317-324 - Takashi Tokuda
CMOS LSI-based multi-chip flexible retinal prosthesis device for subretinal implantation. 325-328 - Young-Jae Min, Soo-Won Kim:
A CMOS TDC-based digital magnetic Hall sensor using the self temperature compensation. 329-332 - Jeremy Holleman, Apurva Mishra, Chris Diorio, Brian P. Otis:
A micro-power neural spike detector and feature extractor in .13μm CMOS. 333-336 - Frederic Nabki
A compact and programmable high-frequency oscillator based on a MEMS resonator. 337-340
Session 14 - Advanced SoCs - techniques and applications
- Steven J. E. Wilton, Arif Rahman:
Session 14 - Advanced SoCs - techniques and applications. - Kevin J. Nowka
Characterization and design for variability and reliability. 341-346 - JunYoung Park, Joshua Jaeyoung Kang, Sunghyun Park, Michael P. Flynn:
A 9Gbit/s serial transceiver for on-chip global signaling over lossy transmission lines. 347-350 - Ting-Chen Wei, Wei-Chang Liu, Chi-Yao Tseng, Syu-Siang Long, Shyh-Jye Jou, Muh-Tian Shiue:
A 28mW OFDM baseband receiver chip for DVB-T/H with all digital synchronization. 351-354 - Noboru Sakimura, Tadahiko Sugibayashi, Ryusuke Nebashi, Naoki Kasai:
Nonvolatile Magnetic Flip-Flop for standby-power-free SoCs. 355-358 - Tino Copani, Bert Vermeire, Anuj Jain, Habib Karaki, Kailash Chandrashekar, Sushmit Goswami, Jennifer Kitchen, Hoon Hee Chung, Ilker Deligoz, Bertan Bakkaloglu
A fully integrated pulsed-LASER time-of-flight measurement system with 12ps single-shot precision. 359-362 - Hong Chen, Chen Jia, Yi Chen, Ming Liu, Chun Zhang, Zhihua Wang:
A low-power IC design for the wireless monitoring system of the orthopedic implants. 363-366 - Kyusik Chung, Chang-Hyo Yu, Donghyun Kim, Lee-Sup Kim:
Tessellation-enabled shader for a bandwidth-limited 3D graphics engine. 367-370
Session 15 - IC Technology - more Moore and more than Moore
- Alvin Loke, Jordan Lai:
Session 15 - IC Technology - more Moore and more than Moore. - Kurt Ronse, Philippe Jansen, Roel Gronheid, Eric Hendrickx, Mireille Maenhoudt, Mieke Goethals, Geert Vandenberghe:
Lithography options for the 32nm half pitch node and beyond. 371-378 - Chris Auth:
45nm high-k + metal gate strain-enhanced CMOS transistors. 379-386 - Patrice Garcia, Alain Chantre, Sébastien Pruvost, Pascal Chevalier
Will BiCMOS stay competitive for mmW applications ? 387-394 - John P. Kent, Jagdish Prasad:
Microelectronics for the real world: "Moore" versus "More than Moore". 395-402
Session 16 - Embedded memory
- Kenji Noda, Jean-Christophe Vial:
Session 16 - Embedded memory. - Mohammed H. Taufique, Alex Okpisz, Haseeb N. Ahmed, John R. Riley, Mohammad M. Hasan, Gianfranco Gerosa:
A 512-KB level-2 cache design in 45-nm for low power IA processor silverthorne. 403-406 - Tony Tae-Hyoung Kim, Jason Liu, Chris H. Kim:
A voltage scalable 0.26V, 64kb 8T SRAM with Vmin lowering techniques and deep sleep mode. 407-410 - Andrew Carlson, Zheng Guo, Liang-Teck Pang, Tsu-Jae King Liu, Borivoje Nikolic
Compensation of systematic variations through optimal biasing of SRAM wordlines. 411-414 - Umut Arslan, Mark P. McCartney, Mudit Bhargava, Xin Li, Ken Mai
Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines. 415-418 - Myeong-Eun Hwang, Kaushik Roy:
A 135mV 0.13μW process tolerant 6T subthreshold DTMOS SRAM in 90nm technology. 419-422 - Mingoo Seok, Scott Hanson, Jae-sun Seo, Dennis Sylvester, David T. Blaauw:
Robust ultra-low voltage ROM design. 423-426 - Nan Wang, Xiang Yao, Yu Lei, Guoyou Feng, Qiaohua Dong, Liang Xu, Lu Guo, Zi Wang, T. S. Tang:
A million cycle 0.13um 1Mb embedded SONOS Flash memory using Successive Approximated Read Calibration. 427-430
Session 17 - Clocking circuits
- Dennis Michael Fischette, Kimo Tam:
Session 17 - Clocking circuits. - Alexander V. Rylyakov, José A. Tierno, George English, Michael A. Sperling, Daniel J. Friedman:
A wide tuning range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45nm SOI. 431-434 - Ting Wu, Xudong Shi, Kambiz Kaviani, Haechang Lee, Jung-Hoon Chun, T. J. Chin, Jie Shen, Rich Perego, Ken Chang:
Clocking circuits for a 16Gb/s memory interface. 435-438 - Sander Gierkink:
A 1V 15.6mW 1-2GHz -119dBc/Hz @ 200kHz clock multiplying DLL. 439-442 - Abhijith Arakali, Srikanth Gondi, Pavan Kumar Hanumolu:
A 0.5-to-2.5GHz supply-regulated PLL with noise sensitivity of -28dB. 443-446 - Masum Hossain, Anthony Chan Carusone
20 GHz low power QVCO and De-skew techniques in 0.13μm digital CMOS. 447-450 - Fabio Pareschi
A 3 GHz Spread Spectrum Clock Generator for SATA applications using chaotic PAM modulation. 451-454 - Minyoung Song
A 1.5 GHz spread spectrum clock generator with a 5000ppm piecewise linear modulation. 455-458 - Ankur Agrawal, Pavan Kumar Hanumolu, Gu-Yeon Wei:
A 8×5 Gb/s source-synchronous receiver with clock generator phase error correction. 459-462
Session 18 - Millimeter-wave circuit techniques
- Payam Heydari, Nobuyuki Itoh:
Session 18 - Millimeter-wave circuit techniques. - Tian-Wei Huang, Huei Wang:
Millimeter-wave CMOS integrated circuits for gigabit WPAN applications. 463-470 - Alexander Tomkins, Ricardo Andres Aroca, Takuji Yamamoto, Sean T. Nicolson, Yoshiyasu Doi, Sorin P. Voinigescu:
A zero-IF 60GHz transceiver in 65nm CMOS with ≫ 3.5Gb/s links. 471-474 - Laurence Moquillon, Patrice Garcia, Sébastien Pruvost, Stéphane Le Tual, Maxime Marchetti, Laurent Chabert, Nicole Bertholet, Angelo Scuderi, Salvatore Scaccianoce, Alberto Serratore, Nicolo Ivan Piazzese, Cedric Dehos, Dominique Morche:
Low-cost fully integrated BiCMOS transceiver for pulsed 24-GHz automotive radar sensors. 475-478 - Chao-Shiun Wang, Juin-Wei Huang, Kun-Da Chu, Chorng-Kuang Wang:
A 0.13μm CMOS fully differential receiver with on-chip baluns for 60GHz broadband wireless communications. 479-482 - Shon-Hang Wen, Chao-Shiun Wang, Chorng-Kuang Wang:
A low power 20 GHz 1.5 Gb/s CMOS injection-pulling FSK modulator and frequency discriminator for 60GHz links. 483-486 - Vipul Jain, Babak Javid, Payam Heydari:
A 24/77GHz dual-band BiCMOS frequency synthesizer. 487-490 - Xuefeng Yu, Fa Foster Dai, Dayu Yang, J. David Irwin, Richard C. Jaeger:
An X/Ku-band frequency synthesizer using a 9-Bit quadrature DDS. 491-494 - Xiaolei Zhu, Yanfei Chen, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Hirotaka Tamura, Sanroku Tsukamoto, Tadahiro Kuroda:
A dynamic offset control technique for comparator design in scaled CMOS technology. 495-498 - Dong-Woo Jee, Seung-Jin Park, Hong-June Park, Jae-Yoon Sim:
A low-voltage OP amp with digitally controlled algorithmic approximation. 499-502 - Yi-Gyeong Kim, Min-Hyung Cho, Kwi-Dong Kim, Jong-Kee Kwon, Jongdae Kim:
A 105.5 dB, 0.49 mm2 Audio ΣΔ modulator using chopper stabilization and fully randomized DWA. 503-506 - Yu-Shiang Lin, Dennis Sylvester, David T. Blaauw:
An ultra low power 1V, 220nW temperature sensor for passive wireless applications. 507-510 - Song Guo, Hoi Lee, Philipos C. Loizou:
A 9-Bit configurable current source with enhanced output resistance for cochlear stimulators. 511-514 - Tamer A. Elkhatib
Super-resolution: Imaging beyond the pixel size limit. 515-518 - Jorge Varona
Polysilicon vertical actuator powered with waste heat. 519-522 - Peng Cong, Wen H. Ko, Darrin J. Young:
Low noise μWatt interface circuits for wireless implantable real-time digital blood pressure monitoring. 523-526 - Tzu-Chieh Kuo, Alan N. Willson Jr.:
A flexible decoder IC for WiMAX QC-LDPC codes. 527-530 - Ping-Hsuan Hsieh
Minimizing the supply sensitivity of CMOS ring oscillator by jointly biasing the supply and control voltage. 531-534 - Peter R. Wilson, Reuben Wilcock, Iain McNally, Matthew Swabey, Bashir M. Al-Hashimi:
The Superchip: Innovative teaching of IC design and manufacture. 535-538 - Jae-Sung Yoon, Donghyun Kim, Chang-Hyo Yu, Lee-Sup Kim:
A 3D graphics processor with fast 4D vector inner product units and power aware texture cache. 539-542 - Michael Wieckowski, Young Min Park, Carlos Tokunaga
Timing yield enhancement through soft edge flip-flop based design. 543-546 - Yasumi Nakamura, David Levacq, Limin Xiao, Takuya Minakawa, Taro Niiyama, Makoto Takamiya, Takayasu Sakurai:
1/5 power reduction by global optimization based on fine-grained body biasing. 547-550 - Sunghwa Ok, Jungmoon Kim, Gilwon Yoon, Hyunho Chu, Jaegeun Oh, Seon Wook Kim, Chulwoo Kim:
A DC-DC converter with a dual VCDL-based ADC and a self-calibrated DLL-based clock generator for an energy-aware EISC processor. 551-554 - Enrico Dallago, Daniele Miatton, Giuseppe Venchi, Valeria Bottarel, Giovanni Frattini, Giulio Ricotti, Monica Schipani:
Active autonomous AC-DC converter for Piezoelectric Energy Scavenging Systems. 555-558 - Simone Erba, Massimo Pozzoni, Matteo Pisati, Riccardo Brama
A 10Gb/s receiver with linear backplane equalization and mixer-based self-aligned CDR. 559-562 - Hayun Chung, Andrew Liu, Gu-Yeon Wei:
A 12.5-Gbps, 7-bit transmit DAC with 4-tap LUT-based equalization in 0.13μm CMOS. 563-566 - Lin Zhang, Berkehan Ciftcioglu, Hui Wu:
Active deskew in injection-locked clocking. 567-570 - Raffaella Genesi, Francesco M. De Paola
A 53 GHz DCO for mm-wave WPAN. 571-574 - Nathan M. Neihart, David J. Allstot, Matt Miller, Pat Rakers:
Twisted inductors for low coupling mixed-signal and RF applications. 575-578 - Flavio Avanzo, Francesco M. De Paola
A common-base linear rf power amplifier for 3G cellular applications. 579-582 - Kuan-Yu Lin, Mourad N. El-Gamal:
Design of low power CMOS ultra-wideband 3.1-10.6 GHz pulse-based transmitters. 583-586
Session 19 - Low power and non-traditional RF tranceivers
- Ramesh Harjani, Andrea Mazzanti:
Session 19 - Low power and non-traditional RF tranceivers. - John R. Long, Wanghua Wu, Yunzhi Dong, Yi Zhao, Mihai A. T. Sanduleanu
Energy-efficient wireless front-end concepts for ultra lower power radio. 587-590 - James Ayers, Kartikeya Mayaram, Terri S. Fiez:
A 0.4 nJ/b 900MHz CMOS BFSK super-regenerative receiver. 591-594 - Napong Panitantum, Kartikeya Mayaram, Terri S. Fiez:
A 900-MHz low-power transmitter with fast frequency calibration for wireless sensor networks. 595-598 - Yao-Hong Liu
A 3.5-mW 15-Mbps O-QPSK transmitter for real-time wireless medical imaging applications. 599-602 - Jongsik Kim, Seungsoo Kim, Jaewook Shin, Youngcho Kim, Junki Min, Kihong Kim, Hyunchol Shin:
A CMOS direct conversion transmitter with integrated in-band harmonic suppression for IEEE 802.22 cognitive radio applications. 603-606 - Robert F. Wiser, Masoud Zargari, David K. Su, Bruce A. Wooley:
A 5-GHz wireless LAN transmitter with integrated tunable high-Q RF filter. 607-610
Session 20 - Advanced wireline techniques
- Ed van Tuijl, Ken Chang:
Session 20 - Advanced wireline techniques. - Mike Bichan, Anthony Chan Carusone
A 6.5 Gb/s backplane transmitter with 6-tap FIR equalizer and variable tap spacing. 611-614 - Behzad Razavi:
Phase-locking in wireline systems: Present and future. 615-622 - Rick A. Philpott, James S. Humble, Robert A. Kertis, Karl E. Fritz, Barry K. Gilbert, Erik S. Daniel:
A 20Gb/s SerDes transmitter with adjustable source impedance and 4-tap feed-forward equalization in 65nm bulk CMOS. 623-626 - Daeik D. Kim, Choongyeun Cho, Jonghae Kim, Jean-Olivier Plouchart:
Wideband mmWave CML static divider in 65nm SOI CMOS technology. 627-634 - Horace Cheng, Anthony Chan Carusone
A 32/16 Gb/s 4/2-PAM transmitter with PWM pre-Emphasis and 1.2 Vpp per side output swing in 0.13-μm CMOS. 635-638 - Kwang-Il Oh, Lee-Sup Kim, Kwang-Il Park, Young-Hyun Jun, Kinam Kim:
A 5-Gb/s/pin transceiver for DDR memory interface with a crosstalk suppression scheme. 639-642 - Jean-Michel Redoute
EMI resisting smart-power integrated LIN driver with reduced slope pumping. 643-646
Session 21 - Leveraging the third Dimension
- Rakesh H. Patel, Michael Seningen:
Session 21 - Leveraging the third Dimension. - Nobuaki Miyakawa, Eiri Hashimoto, Takanori Maebashi, Natsuo Nakamura, Yutaka Sacho, Shigeto Nakayama, Shinjiro Toyoda:
Stacking technology based on 8-inch wafers using direct connection between TSV and micro-bump. 647-650 - Vasilis F. Pavlidis, Ioannis Savidis, Eby G. Friedman:
Clock distribution networks for 3-D ictegrated Circuits. 651-654 - Christopher Mineo, Ravi Jenkal, Samson Melamed
Inter-die signaling in three dimensional integrated circuits. 655-658 - Filipp Akopyan, Carlos Tadeo Ortega Otero, David Fang, Sandra J. Jackson, Rajit Manohar:
Variability in 3-D integrated circuits. 659-662 - Muhannad S. Bakir, Calvin King, Deepak C. Sekar, Hiren D. Thacker, Bing Dang, Gang Huang, Azad Naeemi
3D heterogeneous integrated systems: Liquid cooling, power delivery, and implementation. 663-670 - Giuseppe Li Puma, Ernst Kristan, Paolo De Nicola, Cyril Vannier, Braam Greyling, Salvatore Piccolella:
SiP for GSM/EDGE in CMOS technology. 671-674 - Hiroyuki Kondo, Masami Nakajima, Sugako Otani, Osamu Yamamoto, Norio Masui, Naoto Okumura, Mamoru Sakugawa, Masaya Kitao, Koichi Ishimi, Masayuki Sato, Fumitaka Fukuzawa, Kazuhiro Inaoka, Yoshihiro Saito, Kazutami Arimoto, Toru Shimizu:
Heterogeneous multicore SoC for secure multimedia applications. 675-678 - Joohyun Lee, Sungdo Kim, Jinkyu Kim, Duckhwan Kim, Young-Su Kwon, Minseok Choi, Kihyuk Park, Bontae Koo, Nak-Woong Eum, Hyuckjae Lee:
A 159.2mW SoC implementation of T-DMB receiver including stacked memories. 679-682
Session 22 - Noise and oscillator simulation
- Colin C. McAndrew, Larry Nagel:
Session 22 - Noise and oscillator simulation. - Liuchun Cai, Ramesh Harjani:
Modeling, measurement and mitigation of crosstalk noise coupling in 3D-ICs. 683-686 - Mikiko Sode Tanaka, Mikihiro Kajita, Naoya Nakayama, Satoshi Nakamoto:
A method using circuit/substrate macro modeling to analyze substrate noise in a 3.2-GHz 350M-transistor microprocessor. 687-690 - Brian S. Leibowitz, Jaeha Kim, Jihong Ren, Chris J. Madden:
Characterization of random decision errors in clocked comparators. 691-694 - Igor Vytyaz, Josh Carnes, Ting Wu, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram:
Noise tolerant oscillator design using perturbation projection vector analysis. 695-698 - Mozhgan Mansuri, Frank O'Mahony, Ganesh Balamurugan, James E. Jaussi, Joseph T. Kennedy, Sudip Shekhar, Randy Mooney, Bryan Casper:
Strong injection locking of low-Q LC oscillators. 699-702
Session 23 - Analog techniques
- Don Thelen, Ken Suyama:
Session 23 - Analog techniques. - Manisha Gambhir, Vijay Dhanasekaran, José Silva-Martínez, Edgar Sánchez-Sinencio:
A low power 1.3GHz dual-path current mode Gm-C filter. 703-706 - Peter Kurahashi, Pavan Kumar Hanumolu, Un-Ku Moon:
A 1V downconversion filter using duty-cycle controlled bandwidth tuning. 707-710 - Joshua Jaeyoung Kang, David T. Lin, Li Li, Michael P. Flynn:
A reconfigurable FIR filter embedded in a 9b successive approximation ADC. 711-714 - Peter R. Kinget
Voltage references for ultra-low supply voltages. 715-720 - Ting-Chou Lu, Ming-Dou Ker, Hsiao-Wen Zan, Chun-Hung Kuo, Chun-Huai Li, Yao-Jen Hsieh, Chun-Ting Liu:
Design of bandgap voltage reference circuit with all TFT devices on glass substrate in a 3-μm LTPS process. 721-724 - William P. Evans, David Burnell:
Deep submicron effects on data converter building blocks. 725-728
Session 24 - Advanced subsystems for connectivity and cellular radio.
- Stefan Drude, Earl W. McCune Jr.:
Session 24 - Advanced subsystems for connectivity and cellular radio. - Namsoo Kim, Lawrence E. Larson, Vladimir Aparin:
A highly linear SAW-less CMOS receiver using a mixer with embedded Tx filtering for CDMA. 729-732 - Manel Collados, Paul T. M. van Zeijl, Nenad Pavlovic:
High-power digital envelope modulator for a polar transmitter in 65nm CMOS. 733-736 - Jason T. Stauth
A 2.4GHz, 20dBm class-D PA with single-bit digital polar modulation in 90nm CMOS. 737-740 - Larry Larson, Donald F. Kimball, Peter M. Asbeck:
Linearity and efficiency enhancement strategies for 4G wireless power amplifier designs. 741-748 - Ping-Ying Wang, Jing-Hong Conan Zhan, Hsiang-Hui Chang, Bing-Yu Hsieh:
An analog enhanced all digtial RF fractional-N PLL with self-calibrated capability. 749-752 - Xueyi Yu, Yuanfeng Sun, Woogeun Rhee
A ΔΣ fractional-N synthesizer with customized noise shaping for WCDMA/HSDPA applications. 753-756
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