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DATE 2005: Munich, Germany
- 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany. IEEE Computer Society 2005, ISBN 0-7695-2288-2
Volume 1
Keynote Addresses
- Jeong-Taek Kong:
SoC in Nanoera: Challenges and Endless Possibility. 2 - Garry Hughes:
Striking a New Balance in the Nanometer Era: First-Time-Right and Time-to-Market Demands Versus Technology Challenges. 3
1A: Partitioning and Optimisation for Reconfigurable Computing
- Nastaran Baradaran, Pedro C. Diniz:
A Register Allocation Algorithm in the Presence of Scalar Replacement for Fine-Grain Configurable Architectures. 6-11 - Yoonjin Kim, Mary Kiemb, Chulsoo Park, Jinyong Jung, Kiyoung Choi:
Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization. 12-17 - Roman L. Lysecky, Frank Vahid:
A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning. 18-23 - Ray C. C. Cheung
, Wayne Luk, Peter Y. K. Cheung:
Reconfigurable Elliptic Curve Cryptosystems on a Chip. 24-29
Interactive Presentations
- Rui Rodrigues, João M. P. Cardoso
An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs. 30-31 - N. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin:
FPGA Architecture for Multi-Style Asynchronous Logic. 32-33
1B: Hot Topic - Analogue/Digital Circuit Design in 65nm: End of the Road
- Georges G. E. Gielen
Analog and Digital Circuit Design in 65 nm CMOS: End of the Road? 36-42
1C: SoC Design-for-Test
- Sandeep Kumar Goel, Erik Jan Marinissen
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips. 44-49 - Anuja Sehgal, Fang Liu, Sule Ozev, Krishnendu Chakrabarty
Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores. 50-55 - Matthias Beck, Olivier Barondeau, Martin Kaibel, Frank Poehl, Xijiang Lin, Ron Press:
Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality. 56-61
Interactive Presentation
- Alexandre M. Amory
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture. 62-63
1E: Embedded Tutorial - Cross-Pollination between HW and SW - Hard Lessons for Software, and Vice Versa
- Stephen A. Edwards
The Challenges of Hardware Synthesis from C-Like Languages. 66-67 - Alexander G. Dean:
Software Thread Integration and Synthesis for Real-Time Applications. 68-69 - Ian Oliver:
Applying UML and MDA to Real Systems Design. 70-71
1F: Low Power Design with Error Tolerance
- Diana Marculescu
Energy Bounds for Fault-Tolerant Nanoscale Designs. 74-79 - Himanshu Kaul, Dennis Sylvester, David T. Blaauw, Trevor N. Mudge, Todd M. Austin:
DVS for On-Chip Bus Designs Based on Timing Error Correction. 80-85 - Le Cai, Yung-Hsiang Lu:
Joint Power Management of Memory and Disk. 86-91 - Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin:
Assertion-Based Design Exploration of DVS in Network Processor Architectures. 92-97
2A: Scheduling and Synthesis for Reconfigurable Computin
- Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis:
Instruction Scheduling for Dynamic Hardware Configurations. 100-105 - Javier Resano
A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware. 106-111 - Zhi Guo, Betul Buyukkurt, Walid A. Najjar
Optimized Generation of Data-Path from C Codes for FPGAs. 112-117
2B: Analogue Simulation, Placement and Statistical Analysis
- Ewout Martens, Georges G. E. Gielen
Time-Domain Simulation of Sampled Weakly Nonlinear Systems Using Analytical Integration and Orthogonal Polynomial Series. 120-125 - Fang Liu, Jacob J. Flomenberg, Devaka V. Yasaratne, Sule Ozev:
Hierarchical Variance Analysis for Analog Circuits Based on Graph Modelling and Correlation Loop Tracing. 126-131 - Hratch Mangassarian, Mohab Anis:
On Statistical Timing Analysis with Inter- and Intra-Die Variations. 132-137 - Raoul F. Badaoui, Ranga Vemuri
Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis. 138-143
2C: Analogue and Gigahertz Test
- Koichiro Noguchi, Makoto Nagata
On-Chip Multi-Channel Waveform Monitoring for Diagnostics of Mixed-Signal VLSI Circuits. 146-151 - David C. Keezer
Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL. 152-157 - Marcelo Negreiros
Noise Figure Evaluation Using Low Cost BIST. 158-163 - Sounil Biswas, Peng Li, R. D. (Shawn) Blanton, Larry T. Pileggi:
Specification Test Compaction for Analog Circuits and MEMS. 164-169
Interactive Presentations
- Rabeb Kheriji, V. Danelon, Jean-Louis Carbonéro, Salvador Mir:
Optimising Test Sets for a Low Noise Amplifier with a Defect-Oriented Approach. 170-171 - Pekka Syri, Juha Häkkinen
IEEE 1149.4 Compatible ABMs for Basic RF Measurements. 172-173 - Carlos Eduardo Savioli, Claudio C. Czendrodi, José Vicente Calvano, Antonio Carneiro de Mesquita Filho:
Fault-Trajectory Approach for Fault Diagnosis on Analog Circuits. 174-175
2E: Ubiquitous Computing: Security and Energy Aspects
- Divya Arora, Srivaths Ravi, Anand Raghunathan
Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring. 178-183 - Jung-Chun Kao, Radu Marculescu
Energy-Aware Routing for E-Textile Applications. 184-189 - Arijit Ghosh, Tony Givargis:
LORD: A Localized, Reactive and Distributed Protocol for Node Scheduling in Wireless Sensor Networks. 190-195 - Bruno Bougard, Francky Catthoor, Denis C. Daly, Anantha P. Chandrakasan, Wim Dehaene:
Energy Efficiency of the IEEE 802.15.4 Standard in Dense Wireless Microsensor Networks: Modeling and Improvement Perspectives. 196-201
Interactive Presentation
- Vivek Rai, Rabi N. Mahapatra:
Lifetime Modeling of a Sensor Network. 202-203
2F: Power Aware Design in DSM Technology
- José Luis Rosselló, Vicent Canals
A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs. 206-211 - Hassan Hassan, Mohab Anis, Antoine El Daher, Mohamed I. Elmasry:
Activity Packing in FPGAs for Leakage Power Reduction. 212-217 - Suresh Srinivasan, Lin Li, Narayanan Vijaykrishnan:
Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures. 218-223 - Saibal Mukhopadhyay, Swarup Bhunia
Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits. 224-229
Interactive Presentation
- Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin:
Leakage-Aware Interconnect for On-Chip Network. 230-231
3A: Reconfigurability in MPSoC
- Vincent Nollet, Théodore Marescaux, Prabhat Avasare, Jean-Yves Mignolet:
Centralized Run-Time Resource Management in a Network-on-Chip Containing Reconfigurable Hardware Tiles. 234-239 - Austin Hung, William D. Bishop
Symmetric Multiprocessing on Programmable Chips Made Easy. 240-245 - Nicolas Genko, David Atienza
A Complete Network-On-Chip Emulation Framework. 246-251
Interactive Presentation
- Vincent Nollet, Prabhat Avasare, Jean-Yves Mignolet, Diederik Verkest:
Low Cost Task Migration Initiation in a Heterogeneous MP-SoC. 252-253 - Sander Stuijk
Predictable Embedding of Large Data Structures in Multiprocessor Networks-on-Chip. 254-255
3B: Analogue, Mixed-Signal and RF Circuits and Systems
- Paul Muller, Armin Tajalli, Seyed Mojtaba Atarodi
Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit. 258-263 - Hua Tang, Ying Wei, Alex Doboli:
MINLP Based Topology Synthesis for Delta Sigma Modulators Optimized for Signal Path Complexity, Sensitivity and Power Consumption. 264-269 - Charlotte Soens, Geert Van der Plas
Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance. 270-275
Interactive Presentations
- Ludovic Barrandon, Samuel Crand, Dominique Houzet:
Systematic Figure of Merit Computation for the Design of Pipeline ADC. 277-278 - Yu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma, Rob A. Rutenbar
Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters. 279-280
3C: Reliability at the Very Deep Sub-Micron Region
- Smita Krishnaswamy, George F. Viamontes, Igor L. Markov, John P. Hayes:
Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices. 282-287 - Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee:
Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits. 288-293 - Osama Neiroukh, Xiaoyu Song:
Improving the Process-Variation Tolerance of Digital Circuits Using Gate Sizing and Statistical Techniques. 294-299 - Jonathan R. Carter, Sule Ozev, Daniel J. Sorin:
Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown. 300-305
Interactive Presentations
- Ghazanfar Asadi
An Accurate SER Estimation Method Based on Propagation Probability. 306-307 - Celia López-Ongil
Techniques for Fast Transient Fault Grading Based on Autonomous Emulation. 308-309
3F: HW/SW Solutions for Low Power Multimedia Systems
- Arne Hamann, Rolf Ernst:
TDMA Time Slot and Turn Optimization with Evolutionary Search Techniques. 312-317 - Jennifer L. Wong
Scheduling of Soft Real-Time Systems for Context-Aware Applications. 318-323 - Fernando Rincón
Model Reuse through Hardware Design Patterns. 324-329 - Amr Talaat Abdel-Hamid, Sofiène Tahar, El Mostapha Aboulhamid:
A Public-Key Watermarking Technique for IP Designs. 330-335
Interactive Presentation
- Philippe Martin:
Design of a Virtual Component Neutral Network-on-Chip Transaction Layer. 336-337
3F: HW/SW Solutions for Low Power Multimedia Systems
- Shrirang M. Yardi, Michael S. Hsiao, Thomas L. Martin, Dong S. Ha:
Quality-Driven Proactive Computation Elimination for Power-Aware Multimedia Processing. 340-345 - Ali Iranli, Hanif Fatemi, Massoud Pedram:
HEBS: Histogram Equalization for Backlight Scaling. 346-351 - Ümit Y. Ogras
Energy- and Performance-Driven NoC Communication Architecture Synthesis Using a Decomposition Approach. 352-357 - Tohru Ishihara
A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors. 358-363
4A: Embedded System Partitioning and Validation
- Benoît Miramond
Design Space Exploration for Dynamically Reconfigurable Architectures. 366-371 - Arshad Jhumka, Stephan Klaus, Sorin A. Huss:
A Dependability-Driven System-Level Design Approach for Embedded Systems. 372-377 - Luciano Lavagno, Claudio Passerone, Vishal Shah, Yosinori Watanabe:
A Time Slice Based Scheduler Model for System Level Design. 378-383 - Jae-Gon Lee
A Prediction Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation. 384-389 - Ambar A. Gadkari, S. Ramesh:
Automated Synthesis of Assertion Monitors using Visual Specifications. 390-395
Interactive Presentation
- Greg Stitt, Frank Vahid:
A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms. 396-397
4B: Logic Synthesis
- Aseem Agarwal, Kaviraj Chopra, David T. Blaauw:
Statistical Timing Based Optimization using Gate Sizing. 400-405 - Maxim Teslenko, Elena Dubrova:
An Efficient Algorithm for Finding Double-Vertex Dominators in Circuit Graphs. 406-411 - Alan Mishchenko, Robert K. Brayton:
SAT-Based Complete Don't-Care Computation for Network Optimization. 412-417 - Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Tiziano Villa, Nina Yevtushenko:
Efficient Solution of Language Equations Using Partitioned Representations. 418-423 - G. Fraidy Bouesse, Marc Renaudin, Sophie Dumont, Fabien Germain:
DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement. 424-429
Interactive Presentations
- Andrés Martinelli, Elena Dubrova:
Bound Set Selection and Circuit Re-Synthesis for Area/Delay Driven Decomposition. 430-431 - Igor L. Markov, Dmitri Maslov:
Uniformly-Switching Logic for Cryptographic Hardware. 432-433 - Guowu Yang, William N. N. Hung, Xiaoyu Song, Marek A. Perkowski:
Exact Synthesis of 3-Qubit Quantum Circuits from Non-Binary Quantum Gates Using Multiple-Valued Logic and Group Theory. 434-435
4C: Defect Detection and Characterisation
- Ananta K. Majhi, Mohamed Azimane, Guido Gronthoud, Maurice Lousberg, Stefan Eichenberger, Fred Bowen:
Memory Testing Under Different Stress Conditions: An Industrial Evaluation. 438-443 - Irith Pomeranz, Sudhakar M. Reddy:
Worst-Case and Average-Case Analysis of n-Detection Test Sets. 444-449 - Huaxing Tang, Gang Chen, Sudhakar M. Reddy, Chen Wang, Janusz Rajski, Irith Pomeranz:
Defect Aware Test Patterns. 450-455 - Eric Liau, Doris Schmitt-Landsiedel:
Computational Intelligence Characterization Method of Semiconductor Device. 456-461
Interactive Presentations
- Laurent Lopez, Jean-Michel Portal, Didier Née:
A New Embedded Measurement Structure for eDRAM Capacitor. 462-463 - Sebastià A. Bota
Smart Temperature Sensor for Thermal Testing of Cell-Based ICs. 464-465
4E: Real-Time Scheduling
- Chuan-Yue Yang, Jian-Jia Chen
An Approximation Algorithm for Energy-Efficient Scheduling on A Chip Multiprocessor. 468-473 - Haisang Wu, Binoy Ravindran
Energy-Efficient, Utility Accrual Real-Time Scheduling Under the Unimodal Arbitrary Arrival Model. 474-479 - Rafik Henia, Rolf Ernst:
Context-Aware Scheduling Analysis of Distributed Systems with Tree-Shaped Task-Dependencies. 480-485 - Samarjit Chakraborty
A New Task Model for Streaming Applications and Its Schedulability Analysis. 486-491 - Karsten Albers, Frank Slomka:
Efficient Feasibility Analysis for Real-Time Systems with EDF Scheduling. 492-497
Interactive Presentation
- He Hai, Zhong Yi-fang, Cai Chi-lan:
Unified Modeling of Complex Real-Time Control Systems. 498-499
4F: SoC Power Optimisation
- César A. M. Marcon
Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique. 502-507 - Mirko Loghi, Massimo Poncino:
Exploring Energy/Performance Tradeoffs in Shared Memory MPSoCs: Snoop-Based Cache Coherence vs. Software Solutions. 508-513 - Alexandru Andrei, Marcus T. Schmitz, Petru Eles, Zebo Peng, Bashir M. Al-Hashimi:
Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints. 514-519 - Mirko Loghi, Paolo Azzoni, Massimo Poncino:
Tag Overflow Buffering: An Energy-Efficient Cache Architecture. 520-525
Interactive Presentations
- Min Li, Xiaobo Wu, Richard Yao, Xiaolang Yan:
Q-DPM: An Efficient Model-Free Dynamic Power Management Technique. 526-527 - Joel Coburn, Srivaths Ravi, Anand Raghunathan
Hardware Accelerated Power Estimation. 528-529
4G: Embedded Tutorial - Platforms and Tools for Automotive System Design
- Alberto L. Sangiovanni-Vincentelli
Integrated Electronics in the Car and the Design Chain Evolution or Revolution? 532-533 - Horst Brinkmeyer:
A New Approach to Component Testing. 534-535 - Thomas Illgen, Stefan Ortmann:
Process Oriented Software Quality Assurance - An Experience Report in Process Improvement - OEM Perspective. 536-537 - Joachim Langenwalter:
Embedded Automotive System Development Process. 538-539
5A: System Level Languages, Verification and Simulation
- Samar Abdi, Daniel D. Gajski:
Functional Validation of System Level Static Scheduling. 542-547 - Shuqing Zhao, Daniel D. Gajski:
Defining an Enhanced RTL Semantics. 548-553 - M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC. 554-559 - Ali Habibi, Sofiène Tahar:
Design for Verification of SystemC Transaction Level Models. 560-565
Interactive Presentations
- Wolfgang Klingauf:
Systematic Transaction Level Modeling of Embedded Systems with SystemC. 566-567 - Sohini Dasgupta, Alexandre Yakovlev
Modeling and Verification of Globally Asynchronous and Locally Synchronous Ring Architectures. 568-569
5B: Panel Session - Semiconductor Industry Disaggregation vs. Reaggregation: Who will be the Shark?
- Yervant Zorian, Bill Frerichs, Dennis Wassung, Jim Ensel, Guri Stark, Mike Gianfagna, Kamalesh N. Ruparel:
Semiconductor Industry Disaggregation vs Reaggregation: Who Will be the Shark? 572
5C: Reliable Memory Design
- Jin-Fu Li, Tsu-Wei Tseng, Chin-Long Wey:
An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories. 574-579 - Luca Schiano, Marco Ottavi
On the Analysis of Reed Solomon Coding for Resilience to Transient/Permanent Faults in Highly Reliable Memories. 580-585 - Gokhan Memik, Mahmut T. Kandemir, Ozcan Ozturk:
Increasing Register File Immunity to Transient Errors. 586-591 - Balkaran S. Gill, Michael Nicolaidis, Francis G. Wolff, Christos A. Papachristou
An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories. 592-597
5E: Execution-Time Analysis
- Lars Wehmeyer, Peter Marwedel:
Influence of Memory Hierarchies on Predictability for Time Constrained Embedded Software. 600-605 - Ingomar Wenzel, Bernhard Rieder, Raimund Kirner
Automatic Timing Model Generation by CFG Partitioning and Model Checking. 606-611 - Claire Burguière, Christine Rochange:
A Contribution to Branch Prediction Modeling in WCET Analysi. 612-617
Interactive Presentations
- Reinhold Heckmann, Christian Ferdinand:
Verifying Safety-Critical Timing and Memory-Usage Properties of Embedded Software by Abstract Interpretation. 618-619
5F: Battery and Current Considerations in CMOS Design
- Jawad Khan, Ranga Vemuri
An Iterative Algorithm for Battery-Aware Task Scheduling on Portable Computing Platforms. 622-627 - Kris Tiri, Ingrid Verbauwhede
Design Method for Constant Power Consumption of Differential Logic Circuits. 628-633 - Lap-Fai Leung, Chi-Ying Tsui
Exploiting Dynamic Workload Variation in Low Energy Preemptive Task Scheduling. 634-639 - Alexandre Verle, Xavier Michel, Nadine Azémard, Philippe Maurine, Daniel Auvergne:
Low Power Oriented CMOS Circuit Optimization Protocol. 640-645
Interactive Presentations
- Takeshi Kitahara, Naoyuki Kawabe, Fumihiro Minami, Katsuhiro Seta, Toshiyuki Furusawa:
Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction. 646-647 - Greg M. Link, Narayanan Vijaykrishnan:
Hotspot Prevention Through Runtime Reconfiguration in Network-On-Chip. 648-649 - Robert Bai, Nam Sung Kim, Taeho Kgil, Dennis Sylvester, Trevor N. Mudge:
Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage. 650-651
5G: Panel Session - Automotive System Architectures
- Jürgen Bortolazzi, J.-L. Maté, J. Becker, C. Morgano:
Automotive System Architectures (Automotive Special Day). 654
5K: Keynote
- Harald Heinecke:
Automotive System Design - Challenges and Potential. 656-657
Volume 2
6A: High-Level Verification
- Vasco M. Manquinho
Effective Lower Bounding Techniques for Pseudo-Boolean Optimization. 660-665 - Madhu K. Iyer, Ganapathy Parthasarathy
Efficient Conflict-Based Learning in an RTL Circuit Constraint Solver. 666-671 - ShengYu Shen, Ying Qin, Sikun Li:
A Faster Counterexample Minimization Algorithm Based on Refutation Analysis. 672-677 - Prabhat Mishra
Functional Coverage Driven Test Generation for Validation of Pipelined Processors. 678-683
Interactive Presentations
- Hossein M. Sheini, Karem A. Sakallah:
Pueblo: A Modern Pseudo-Boolean SAT Solver. 684-685 - Jacob Katz, Ziyad Hanna, Nachum Dershowitz:
Space-Efficient Bounded Model Checking. 686-687 - Gianpiero Cabodi, Marco Crivellari, Sergio Nocco, Stefano Quer
Circuit Based Quantification: Back to State Set Manipulation within Unbounded Model Checking. 688-689
6B: System Modelling with UML
- Tim Schattkowsky
A Model-Based Approach for Executable Specifications on Reconfigurable Hardware. 692-697 - Alexandre Chureau, Yvon Savaria, El Mostapha Aboulhamid:
The Role of Model-Level Transactors and UML in Functional Prototyping of Systems-on-Chip: A Software-Radio Application. 698-703 - Elvinia Riccobene
A SoC Design Methodology Involving a UML 2.0 Profile for SystemC. 704-709 - Petri Kukkala, Jouni Riihimäki, Marko Hännikäinen, Timo D. Hämäläinen, Klaus Kronlöf:
UML 2.0 Profile for Embedded System Design. 710-715
Interactive Presentations
- Yves Vanderperren, Wim Dehaene:
UML 2 and SysML: An Approach to Deal with Complexity in SoC/NoC Design. 716-717 - Waseem Ahmed, Doug Myers:
Design Refinement for Efficient Cluste ing of Objects in Embedded Systems. 718-719
6C: Hot Topic - Challenges in Embedded Memory Design and Test
- Erik Jan Marinissen
Challenges in Embedded Memory Design and Test. 722-727
6E: Parallel and Multithreaded Processor Architectures
- Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar:
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures. 730-735 - Francesco Poletti, Antonio Poggiali, Paul Marchal:
Flexible Hardware/Software Support for Message Passing on a Distributed Shared Memory Architecture. 736-741 - André C. Nácul, Tony Givargis:
Lightweight Multitasking Support for Embedded Systems using the Phantom Serializing Compiler. 742-747
Interactive Presentation
- Domenico Barretta, William Fornaciari
Multithreaded Extension to Multicluster VLIW Processors for Embedded Applications. 748-749
6F: Very Deep Submicron Simulation
- Zhao Li, Chuanjin Richard Shi:
An Efficiently Preconditioned GMRES Method for Fast Parasitic-Sensitive Deep-Submicron VLSI Circuit Simulation. 752-757 - Bharat B. Sukhwani, Uday Padmanabhan, Janet Meiling Wang:
Nano-Sim: A Step Wise Equivalent Conductance based Statistical Simulator for Nanotechnology Circuit Design. 758-763 - Kunhyuk Kang, Bipul Chandra Paul, Kaushik Roy:
Statistical Timing Analysis using Levelized Covariance Propagation. 764-769 - Y. Satish Kumar
A Probabilistic Collocation Method Based Statistical Gate Delay Model Considering Process Variations and Multiple Input Switching. 770-775
Interactive Presentation
- Shahin Nazarian, Massoud Pedram, Emre Tuncer, Tao Lin, Amir H. Ajami:
Modeling and Propagation of Noisy Waveforms in Static Timing Analysis. 776-777
6G: SoC Prototyping and Simulation
- Shankar Mahadevan, Federico Angiolini, Michael Storgaard, Rasmus Grøndahl Olsen, Jens Sparsø
A Network Traffic Generator Model for Fast Network-on-Chip Simulation. 780-785 - Mehrdad Reshadi, Nikil D. Dutt
Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation. 786-791 - Jürgen Schnerr, Oliver Bringmann, Wolfgang Rosenstiel:
Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs. 792-797 - Franco Fummi, Mirko Loghi, Stefano Martini, Marco Monguzzi, Giovanni Perbellini, Massimo Poncino:
Virtual Hardware Prototyping through Timed Hardware-Software Co-Simulation. 798-803
Interactive Presentation
- Oreste Villa, Patrick Schaumont
Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip. 804-805
7A: Memory Optimisation and Clocking for SoC
- Ilya Issenin, Nikil D. Dutt
FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations. 808-813 - Ozcan Ozturk, Mahmut T. Kandemir:
Nonuniform Banking for Reducing Memory Energy Consumption. 814-819 - Vinil Varghese, Tom Chen, Peter Michael Young:
Systematic Analysis of Active Clock Deskewing Systems Using Control Theory. 820-825
Interactive Presentations
- Sankalp Kallakuri, Alex Doboli, Eugene A. Feinberg:
Buffer Insertion for Bridges and Optimal Buffer Sizing for Communication Sub-System of Systems-on-Chip. 826-827 - Hanlai Pu, Ling Ming, Jin Jing:
Extended Control Flow Graph Based Performance Optimization Using Scratch-Pad Memory. 828-829
7B: Embedded Tutorial - UML for System-on-Chip Design: Current Applications and Future Perspectives
- Tim Schattkowsky
UML 2.0 - Overview and Perspectives in SoC Design. 832-833 - Stephen J. Mellor, John R. Wolfe, Campbell McCausland:
Why Systems-on-Chip Needs More UML like a Hole in the Head. 834-835 - Qiang Zhu, Ryosuke Oishi, Takashi Hasegawa, Tsuneo Nakata:
Integrating UML into SoC Design Process. 836-837
7C: Test Power Reduction and Diagnosis
- Paul M. Rosinger, Bashir M. Al-Hashimi, Krishnendu Chakrabarty
Rapid Generation of Thermal-Safe Test Schedules. 840-845 - Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady
Simultaneous Reduction of Dynamic and Static Power in Scan Structures. 846-851 - Baosheng Wang, Yuejian Wu, André Ivanov:
A Fast Diagnosis Scheme for Distributed Small Embedded SRAMs. 852-857
Interactive Presentations
- Ghenadie Bodean, Diana Bodean, A. Labunetz:
New Schemes for Self-Testing RAM. 858-859 - B. Cheon, E. Lee, Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Jin Woo Cho, J. Park, Hao-Jan Chao, Shianling Wu:
At-Speed Logic BIST for IP Cores. 860-861
7E: Scheduling and Memory Optimisation for Multiprocessor Embedded Systems
- Viacheslav Izosimov, Paul Pop
Design Optimization of Time-and Cost-Constrained Fault-Tolerant Distributed Embedded Systems. 864-869 - Mahmut T. Kandemir, Guilin Chen:
Locality-Aware Process Scheduling for Embedded MPSoCs. 870-875 - Torsten Kempf, Malte Doerper, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tim Kogel, Bart Vanthournout:
A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms. 876-881 - Ozcan Ozturk, Hendra Saputra, Mahmut T. Kandemir, Ibrahim Kolcu:
Access Pattern-Based Code Compression for Memory-Constrained Embedded Systems. 882-887 - Ryan Mannion, Harry Hsieh, Susan Cotterell, Frank Vahid:
System Synthesis for Networks of Programmable Blocks. 888-893
Interactive Presentations
- Thilo Streichert, Christian Haubelt
Distributed HW/SW-Partitioning for Embedded Reconfigurable Networks. 894-895 - Pierre Bomel, Eric Martin, Emmanuel Boutillon:
Synchronization Processor Synthesis for Latency Insensitive Systems. 896-897 - Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin:
Thermal-Aware Task Allocation and Scheduling for Embedded Systems. 898-899
7F: Layout Issues
- Kristofer Vorwerk, Andrew A. Kennings:
An Improved Multi-Level Framework for Force-Directed Placement. 902-907 - Charles C. Chiang, Andrew B. Kahng, Subarna Sinha, Xu Xu, Alexander Zelikovsky
Bright-Field AAPSM Conflict Detection and Correction. 908-913 - Hua Wang, Miguel Miranda, Wim Dehaene, Francky Catthoor, Karen Maex:
Systematic Analysis of Energy and Delay Impact of Very Deep Submicron Process Variability Effects in Embedded SRAM Modules. 914-919
Interactive Presentations
- Christophe Alexandre, Hugo Clément, Jean-Paul Chaput, Marek Sroka, Christian Masson, Remy Escassut:
TSUNAMI: An Integrated Timing-Driven Place And Route Research Platform. 920-921 - Amitava Bhaduri, Ranga Vemuri
Inductive and Capacitive Coupling Aware Routing Methodology Driven by a Higher Order RLCK Moment Metric. 922-923
7G: Quantifying Architecture Trade-Off
- Animesh Datta, Swarup Bhunia
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies. 926-931 - Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Dan Cotofana
Compositional Memory Systems for Multimedia Communicating Tasks. 932-937 - Judita Kruse, Clive Thomsen, Rolf Ernst, Thomas Volling, Thomas Spengler
Introducing Flexible Quantity Contracts into Distributed SoC and Embedded System Design Processes. 938-943
Interactive Presentations
- Mario R. Casu
A New System Design Methodology for Wire Pipelined SoC. 944-945 - Minas Dasygenis
A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck. 946-947
8A: Panel Session - Is There a Market for SystemC Tools?
- Wolfgang Rosenstiel, Reinaldo A. Bergamaschi, Frank Ghenassia, Thorsten Groetker, Masamichi Kawarabayashi, Marinus C. van Lier, Albrecht Mayer, Mike Meredith, Mark Milligan, Stuart Swan:
Is there a Market for SystemC Tools? 950
8B: Interconnect Solutions: Timing, Noise, and Process Variations
- Lizheng Zhang, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen:
Statistical Timing Analysis with Extended Pseudo-Canonical Timing Model. 952-957 - Peng Li, Frank Liu, Xin Li, Lawrence T. Pileggi, Sani R. Nassif:
Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction. 958-963 - Praveen Ghanta, Sarma B. K. Vrudhula, Rajendran Panda, Janet Meiling Wang:
Stochastic Power Grid Analysis Considering Process Variations. 964-969 - Jinjun Xiong
Buffer Insertion Considering Process Variation. 970-975 - Baohua Wang, Pinaki Mazumder:
EM Wave Coupling Noise Modeling Based on Chebyshev Approximation and Exact Moment Formulation. 976-981
Interactive Presentations
- Cristiano Forzan, Davide Pandini:
Modeling the Non-Linear Behavior of Library Cells for an Accurate Static Noise Analysis. 982-983 - Ajith Chandy, Tom Chen:
Performance Driven Decoupling Capacitor Allocation Considering Data and Clock Interactions. 984-985 - Paul Zuber, Armin Windschiegl, Raúl Medina Beltrán de Otálora, Walter Stechele, Andreas Herkersdorf:
Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization. 986-987
8C: Advances in Pattern Generation for Fault Detection and Diagnosis
- Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi:
Implicit and Exact Path Delay Fault Grading in Sequential Circuits. 990-995 - Yu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman:
Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs. 996-1001 - Kameshwar Chandrasekar, Michael S. Hsiao:
Integration of Learning Techniques into Incremental Satisfiability for Efficient Path-Delay Fault Test Generation. 1002-1007 - Irith Pomeranz, Sudhakar M. Reddy:
The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits. 1008-1013 - Raja K. K. R. Sandireddy, Vishwani D. Agrawal:
Diagnostic and Detection Fault Collapsing for Multiple Output Circuits. 1014-1019
Interactive Presentations
- Zaid Al-Ars, Said Hamdioui, Georg Mueller, Ad J. van de Goor:
Framework for Fault Analysis and Test Generation in DRAMs. 1020-1021 - Mathieu Scholivé, Vincent Beroulle, Chantal Robach, Marie-Lise Flottes, Bruno Rouzeyre:
Mutation Sampling Technique for the Generation of Structural Test Data. 1022-1023
8E: Embedded Software Technology
- Mahmut T. Kandemir, Feihui Li, Guilin Chen, Guangyu Chen, Ozcan Ozturk:
Studying Storage-Recomputation Tradeoffs in Memory-Constrained Embedded Processing. 1026-1031 - Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin:
BB-GC: Basic-Block Level Garbage Collection. 1032-1037 - Jacques Combaz, Jean-Claude Fernandez, Thierry Lepley, Joseph Sifakis:
Fine Grain QoS Control for Multimedia Application Software. 1038-1043 - Massimo Baleani, Alberto Ferrari, Leonardo Mangeruca, Alberto L. Sangiovanni-Vincentelli
Correct-by-Construction Transformations across Design Environments for Model-Based Embedded Software Development. 1044-1049 - Elaine Cheong, Jie Liu:
galsC: A Language for Event-Driven Embedded Systems. 1050-1055
Interactive Presentations
- Jie S. Hu, Feihui Li, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin:
Compiler-Directed Instruction Duplication for Soft Error Detection. 1056-1057 - Tadashi Takeuchi:
OS Debugging Method Using a Lightweight Virtual Machine Monitor. 1058-1059 - Nikolaos Kavvadias, Spiridon Nikolaidis
Hardware Support for Arbitrarily Complex Loop Structures in Embedded Applications. 1060-1061
8F: Advanced Analogue Performance Modelling
- Abhishek Somani, Partha Pratim Chakrabarti, Amit Patra:
Mixing Global and Local Competition in Genetic Optimization based Design Space Exploration of Analog Circuits. 1064-1069 - Tom Eeckelaert, Trent McConaghy, Georges G. E. Gielen
Efficient Multiobjective Synthesis of Analog Circuits using Hierarchical Pareto-Optimal Performance Hypersurfaces. 1070-1075 - Gerd Vandersteen, Ludwig De Locht, Snezana Jenei, Yves Rolain, Rik Pintelon
Estimating Scalable Common-Denominator Laplace-Domain MIMO Models in an Errors-in-Variables Framework. 1076-1081 - Trent McConaghy, Tom Eeckelaert, Georges G. E. Gielen
CAFFEINE: Template-Free Symbolic Model Generation of Analog Circuits via Canonical Form Functions and Genetic Programming. 1082-1087
Interactive Presentation
- Mengmeng Ding, Ranga Vemuri
A Two-Level Modeling Approach to Analog Circuit Performance Macromodeling. 1088-1089
8G: Hot Topic - Biochips: Principles and Application
- Nicolò Manaresi, Gianni Medoro, Melanie Abonnenc, Vincent Auger, Paul Vulto, Aldo Romani, Luigi Altomare, Marco Tartagni, Roberto Guerrieri:
New Perspectives and Opportunities From the Wild West of Microelectronic Biochips. 1092-1093
9A: Efficient SAT Based Verification
- Malay K. Ganai, Aarti Gupta
Verification of Embedded Memory Systems using Efficient Memory Modeling. 1096-1101 - Feng Lu, Madhu K. Iyer, Ganapathy Parthasarathy
An Efficient Sequential SAT Solver With Improved Search Strategies. 1102-1107 - Zhaohui Fu, Yinlei Yu, Sharad Malik
Considering Circuit Observability Don't Cares in CNF Satisfiability. 1108-1113
9B: Embedded Tutorial - How Do They Manage Designing Complex SoC?
- Chien-Liang Chen, Jiing-Yuan Lin, Youn-Long Lin:
Integration, Verification and Layout of a Complex Multimedia SOC. 1116-1117 - Chung-Jr Lian, Yu-Wen Huang
PEG, MPEG-4, and H.264 Codec IP Development. 1118-1119 - Cheng-Wen Wu
SOC Testing Methodology and Practice. 1120-1121
9C: Test Pattern Compression and Delay Test Schemes
- Ilia Polian, Alejandro Czutro, Bernd Becker
Evolutionary Optimization in Code-Based Test Compression. 1124-1129 - Kedarnath J. Balakrishnan, Nur A. Touba:
Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination. 1130-1135 - Swarup Bhunia
A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application. 1136-1141 - Lei Li, Krishnendu Chakrabarty
Hybrid BIST Based on Repeating Sequences and Cluster Analysis. 1142-1147
9E: Compiler/Architecture Codesign
- Jianjiang Ceng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun:
C Compiler Retargeting Based on Instruction Semantics Models. 1150-1155 - Guilin Chen, Mahmut T. Kandemir, Mustafa Karaköy:
A Constraint Network Based Approach to Memory Layout Optimization. 1156-1161 - Mohammed Javed Absar, Francky Catthoor:
Compiler-Based Approach for Exploiting Scratch-Pad in Presence of Irregular Array Access. 1162-1167 - Elena Dubrova:
Structural Testing Based on Minimum Kernels. 1168-1173
9F: Network-on-Chip Design Flows
- Srinivasan Murali, Giovanni De Micheli
An Application-Specific Design Methodology for STbus Crossbar Generation. 1176-1181 - Kees Goossens, John Dielissen, Om Prakash Gangwal, Santiago González Pestana, Andrei Radulescu, Edwin Rijpkema:
A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification. 1182-1187 - Stergios Stergiou, Federico Angiolini, Salvatore Carta, Luigi Raffo
xpipes Lite: A Synthesis Oriented Design Library For Networks on Chips. 1188-1193
9G: Biochips and Quantum Computing
- Fei Su, Krishnendu Chakrabarty
Yield Enhancement of Digital Microfluidics-Based Biochips Using Space Redundancy and Local Reconfiguration. 1196-1201 - Fei Su, Krishnendu Chakrabarty
Design of Fault-Tolerant and Dynamically-Reconfigurable Microfluidic Biochips. 1202-1207 - Dmitri Maslov, Christina Young, D. Michael Miller, Gerhard W. Dueck:
Quantum Circuit Simplification Using Templates. 1208-1213 - Kyosun Kim, Kaijie Wu, Ramesh Karri
Towards Designing Robust QCA Architectures in the Presence of Sneak Noise Paths. 1214-1219
9K: CMOS-Based Biosensor Arrarys
- Roland Thewes, Christian Paulus, Meinrad Schienle, Franz Hofmann, Alexander Frey, Ralf Brederlow
CMOS-Based Biosensor Arrays. 1222-1223
10A: Efficient Network-on-Chip Architectures
- Tobias Bjerregaard, Jens Sparsø
A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip. 1226-1231 - Wolf-Dietrich Weber, Joe Chou, Ian Swarbrick, Drew Wingard:
A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips. 1232-1237 - Hangsheng Wang, Li-Shiuan Peh, Sharad Malik
A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks. 1238-1243
10B: Architectural Synthesis and Design Space Exploration
- Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement. 1246-1251 - Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida
Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis. 1252-1257 - Suleyman Tosun, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie:
Reliability-Centric High-Level Synthesis. 1258-1263 - Aviral Shrivastava
PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors. 1264-1269
10C: Concurrent Error Detection and Correction
- Sobeeh Almukhaizim, Yiorgos Makris
Concurrent Error Detection in Asynchronous Burst-Mode Controllers. 1272-1277 - Cristiana Bolchini
Reliable System Specification for Self-Checking Data-Paths. 1278-1283 - Hamidreza Hashempour, Luca Schiano, Fabrizio Lombardi:
Evaluation of Error-Resilience for Reliable Compression of Test Data. 1284-1289 - Fernanda Lima Kastensmidt
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs. 1290-1295
10E: Formal Verification of Processor Architecture and DSP Programs
- Christian Jacobi, Kai Weber, Viresh Paruthi, Jason Baumgartner:
Automatic Formal Verification of Fused-Multiply-Add FPUs. 1298-1303 - Panagiotis Manolios
Refinement Maps for Efficient Verification of Processor Models. 1304-1309 - K. C. Shashidhar, Maurice Bruynooghe, Francky Catthoor, Gerda Janssens:
Functional Equivalence Checking for Verification of Algebraic Transformations on Array-Intensive Source Code. 1310-1315
10F: Interconnect Optimisation
- Brock J. LaMeres, Sunil P. Khatri:
Encoding-Based Minimization of Inductive Cross-Talk for Off-Chip Data Transmission. 1318-1323 - Zhuo Li, Weiping Shi:
An O(bn2) Time Algorithm for Optimal Buffer Insertion with b Buffer Types. 1324-1329 - Xun Liu, Yuantao Peng, Marios C. Papaefthymiou:
RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power. 1330-1335
10G: Hot Topic - Silicon Based Biochips
- Raymond Campagnolo:
eMICAM a New Generation of Active DNA Chip with in Situ Electrochemical Detection. 1338-1339 - Kay-Uwe Kirstein, Yue Li, Martin Zimmermann, Cyril Vancura, Tormod Volden, Wan Ho Song, Jan Lichtenberg, Andreas Hierlemann:
Cantilever-Based Biosensors in CMOS Technology. 1340-1341
Volume 3
1D: Media and Signal Processing
- Sebastián López
A High Quality/Low Computational Cost Technique for Block Matching Motion Estimation. 2-7 - Suhaib A. Fahmy
Hardware Acceleration of Hidden Markov Model Decoding for Person Detection. 8-13 - Hendrik Eeckhaut, Harald Devos, Benjamin Schrauwen, Mark Christiaens, Dirk Stroobandt:
A Hardware-Friendly Wavelet Entropy Codec for Scalable Video. 14-19 - Artur Burchard, Ewa Hekstra-Nowacka, Atul Chauhan:
A Real-Time Streaming Memory Controller. 20-25 - Walter Stechele, L. Alvado Cárcel, Stephan Herrmann, J. Lidón Simón:
A Coprocessor for Accelerating Visual Information Processing. 26-31 - Sandro V. Silva, Sergio Bampi
Area and Throughput Trade-Offs in the Design of Pipelined Discrete Wavelet Transform Architectures. 32-37
2D: Secure and Embedded Security Systems
- Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, C. Anguille, Michel Bardouillet, Christian Buatois, Jean-Baptiste Rigaud
Hardware Engines for Bus Encryption: A Survey of Existing Techniques. 40-45 - Daniel Thull, Roberto Sannino:
Performance Considerations for an Embedded Implementation of OMA DRM 2. 46-51 - Alessandro Cilardo, Antonino Mazzeo
A Novel Unified Architecture for Public-Key Cryptography. 52-57 - Kris Tiri, Ingrid Verbauwhede
A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs. 58-63 - Shengqi Yang, Wayne H. Wolf, Narayanan Vijaykrishnan, Dimitrios N. Serpanos
Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach. 64-69 - Zoya Dyka, Peter Langendörfer:
Area Efficient Hardware Implementation of Elliptic Curve Cryptography by Iteratively Applying Karatsuba's Method. 70-75
Interactive Presentations
- Hala A. Farouk, Magdy Saeb
An Improved FPGA Implementation of the Modified Hybrid Hiding Encryption Algorithm (MHHEA) for Data Communication Security. 76-81 - Ramachandran Pradeep, S. Vinay, Sanjay Burman, V. Kamakoti:
FPGA based Agile Algorithm-On-Demand Co-Processor. 82-83
3D: Hot Topic - MPSoC Platforms for Mobile Multimedia
- Wayne H. Wolf:
Multimedia Applications of Multiprocessor Systems-on-Chips. 86-89
4D: Hot Topic - Low-Power Wireless LANs: Past, Present and Future
- Keith Holt:
Wireless LAN: Past, Present, and Future. 92-93 - Raúl Blázquez, Fred S. Lee, David D. Wentzloff, Brian P. Ginsburg
Direct Conversion Pulsed UWB Transceiver Architecture. 94-95 - Tajana Simunic:
Power Saving Techniques for Wireless LANs. 96-97
5D: Wireless Communication and Networking
- Frank Kienle, Torben Brack, Norbert Wehn:
A Synthesizable IP Core for DVB-S2 LDPC Code Decoding. 100-105 - Andrew Duller, Daniel Towner, Gajinder Panesar, Alan Gray, Will Robbins:
picoArray Technology: The Tool's Story. 106-111 - Ioannis Papaefstathiou
Queue Management in Network Processors. 112-117 - Massimo Conti
System Level Analysis of the Bluetooth Standard. 118-123 - Andrés Takach, Bryan Bowyer, Thomas Bollaert:
C Based Hardware Design for Wireless Applications. 124-129 - Andreas Raabe, Blazej Bartyzel, Joachim K. Anlauf, Gabriel Zachmann
Hardware Accelerated Collision Detection - An Architecture and Simulation Results. 130-135
Interactive Presentations
- Hannu Heusala, Jussi Liedes:
Modeling of a Reconfigurable OFDM IP Block Family For an RF System Simulator. 136-137 - Young-Taek Kim, Taehun Kim, Youngduk Kim, Chulho Shin, Eui-Young Chung, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo:
Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture. 138-139
6D: Automotive
- Wayne Lyons:
Meeting the Embedded Design Needs of Automotive Applications. 142-147 - Albrecht Mayer, Harry Siebert, Klaus D. McDonald-Maier
Debug Support, Calibration and Emulation for Multiple Processor and Powertrain Control SoCs. 148-152 - Carl Jeffrey, Reuben Cutajar, Stephen Prosser, M. Lickess, Andrew Richardson
The Integration of On-Line Monitoring and Reconfiguration Functions using IEEE1149.4 Into a Safety Critical Automotive Electronic Control Unit. 153-158 - Pavel Horsky:
LC Oscillator Driver for Safety Critical Applications. 159-164 - Jan Staschulat, Rolf Ernst, Andreas Schulze, Fabian Wolf:
Context Sensitive Performance Analysis of Automotive Applications. 165-170 - Dirk Ziegenbein, Peter Braun, Ulrich Freund, Andreas Bauer, Jan Romberg, Bernhard Schätz:
AutoMoDe - Model-Based Development of Automotive Software. 171-177
Interactive Presentation
- Massimo Conti
SystemC Analysis of a New Dynamic Power Management Architectur. 177-178
7D: Sensors
- Steve Chappell, Alistair Macarthur, Dan Preston, Dave Olmstead, Bob Flint, Chris Sullivan:
Exploiting Real-Time FPGA Based Adaptive Systems Technology for Real-Time Sensor Fusion in Next Generation Automotive Safety Systems. 180-185 - Luca Fanucci
Platform Based Design for Automotive Sensor Conditioning. 186-191 - Paolo Amato, Nicola Cesario, M. Di Meglio, Francesco Pirozzi:
Realization of a Virtual Lambda Sensor on a Fixed Precision System. 192-197 - Claudio Stagni, Carlotta Guiducci, Massimo Lanzoni, Luca Benini
Hardware-Software Design of a Smart Sensor for Fully-Electronic DNA Hybridization Detection. 198-203 - Momchil Milev, Rod Burt:
A Tool and Methodology for AC-Stability Analysis of Continuous-Time Closed-Loop Systems. 204-208
8D: Best of ESSCIRC 2004
- Kay-Uwe Kirstein, Jan Sedivý, Tomi Salo, Christoph Hagleitner, Tobias Vancura, Andreas Hierlemann
A CMOS-Based Tactile Sensor for Continuous Blood Pressure Monitoring. 210-214 - Johannes Sturm
Optical Receiver IC for CD/DVD/Blue-Laser Application. 215-218 - Terje N. Andersen, Atle Briskemyr, Frode Telstø, Johnny Bjørnsen, Thomas E. Bonnerud, Bjørnar Hernes, Øystein Moldsvor:
A 97mW 110MS/s 12b Pipeline ADC Implemented in 0.18mum Digital CMOS. 219-222 - Christoph Sandner, Martin Clara, Andreas Santner, Thomas Hartig, Franz Kuttner:
A 6bit, 1.2GSps Low-Power Flash-ADC in 0.13µm Digital CMOS. 223-226
9D: IP-Reuse and Reconfigurable Systems
- Paolo Bernardi
Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study. 228-233 - Aline Mello, Leandro Möller, Ney Calazans
MultiNoC: A Multiprocessing System Enabled by a Network on Chip. 234-239 - Dan Hillman:
Using Mobilize Power Management IP for Dynamic & Static Power Reduction in SoC at 130 nm. 240-246 - Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis:
A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms. 247-252 - Tero Rissa, Adam Donlin, Wayne Luk:
Evaluation of SystemC Modelling of Reconfigurable Embedded Systems. 253-258 - Michael Ullmann, Wansheng Jin, Jürgen Becker:
Hardware Support for QoS-based Function Allocation in Reconfigurable Systems. 259-264
10D: Design Verification
- Michele Borgatti, Andrea Capello, Umberto Rossi, Jean-Luc Lambert, Imed Moussa, Franco Fummi, Graziano Pravadelli
An Integrated Design and Verification Methodology for Reconfigurable Multimedia Systems. 266-271 - Giuseppe Falconeri, Walid Naifer, Nizar Romdhane:
Common Reusable Verification Environment for BCA and RTL Models. 272-277 - John S. MacBeth, Dietmar Heinz, Ken Gray:
An Assembler Driven Verification Methodology (ADVM). 278-283 - Yasushi Umezawa, Takeshi Shimizu:
A Formal Verification Methodology for Checking Data Integrity. 284-289 - Ali Habibi, Asif Iqbal Ahmed, Otmane Aït Mohamed, Sofiène Tahar:
On the Design and Verification Methodology of the Look-Aside Interface. 290-295
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