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ISSCC 2022: San Francisco, CA, USA
- IEEE International Solid-State Circuits Conference, ISSCC 2022, San Francisco, CA, USA, February 20-26, 2022. IEEE 2022, ISBN 978-1-6654-2800-2
- Dong Yan, Dongsheng Brian Ma:
A Monolithic GaN Direct 48V/1V AHB Switching Power IC with Auto-Lock Auto-Break Level Shifting, Self-Bootstrapped Hybrid Gate Driving, and On-Die Temperature Sensing. 1-3 - Xiaofei Ma, Yan Lu, Wing-Hung Ki
:
A 27W D2D Wireless Power Transfer System with Compact Single-Stage Regulated Class-E Architecture and Adaptive ZVS Control. 1-3 - Yuqi Su, Tony Tae-Hyoung Kim, Bongjin Kim:
FlexSpin: A Scalable CMOS Ising Machine with 256 Flexible Spin Processing Elements for Solving Complex Combinatorial Optimization Problems. 1-3 - Yukun Zhu
A 430GHz CMOS Concurrent Transceiver Pixel Array for High Angular Resolution Reflection-Mode Active Imaging. 1-3 - Nathan M. Monroe, Georgios C. Doqiamis, Robert Stingel, Preston Myers, Xibi Chen, Ruonan Han:
Electronic THz Pencil Beam Forming and 2D Steering for High Angular-Resolution Operation: A 98×98-Unit 265GHz CMOS Reflectarray with In-Unit Digital Beam Shaping and Squint Correction. 1-3 - Shihkai Kuo, Manideep Dunna, Dinesh Bharadia, Patrick P. Mercier
A WiFi and Bluetooth Backscattering Combo Chip Featuring Beam Steering via a Fully-Reflective Phased-Controlled Multi-Antenna Termination Technique Enabling Operation Over 56 Meters. 1-3 - Alessandro Franceschin, Domenico Riccardi
Series-Resonance BiCMOS VCO with Phase Noise of -138dBc/Hz at 1MHz Offset from 10GHz and -190dBc/Hz FoM. 1-3 - Brian T. Vanderpool, Phillip J. Restle, Eric J. Fluhr, Gregory S. Still, Frank Campisano, Ian Carmichael, Eric Marz, Rahul Batra, Richard L. Willaman:
Deterministic Frequency Boost and Voltage Enhancements on the POWER10TM Processor. 1-3 - Haoyi Zhao, Fa Foster Dai:
A 0.97mW 260MS/s 12b Pipelined-SAR ADC with Ring-TDC-Based Fine Quantizer for PVT Robust Automatic Cross-Domain Scale Alignment. 1-3 - Samuel D. Spetalnick, Muya Chang, Brian Crafton, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
A 40nm 64kb 26.56TOPS/W 2.37Mb/mm2RRAM Binary/Compute-in-Memory Macro with 4.23x Improvement in Density and >75% Use of Sensing Dynamic Range. 1-3 - Suneui Park, Seyeon Yoo, Yuhwan Shin, Jeonghyun Lee, Jaehyouk Choi:
A 97fsrms-Jitter and 68-Multiplication Factor, 8.16GHz Ring-Oscillator Injection-Locked Clock Multiplier with Power-Gating Injection-Locking and Background Multi-Functional Digital Calibrator. 1-3 - Tzu-Hsiang Hsu, Guan-Cheng Chen, Yi-Ren Chen, Chung-Chuan Lo, Ren-Shuo Liu, Meng-Fan Chang, Kea-Tiong Tang, Chih-Cheng Hsieh:
A 0.8V Intelligent Vision Sensor with Tiny Convolutional Neural Network and Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique for Image Classification. 1-3 - Tingxu Hu
A 4A 12-to-1 Flying Capacitor Cross-Connected DC-DC Converter with Inserted D>0.5 Control Achieving >2x Transient Inductor Current Slew Rate and 0.73× Theoretical Minimum Output Undershoot of DSD. 1-3 - Win-San Khwa, Yen-Cheng Chiu, Chuan-Jia Jhang, Sheng-Po Huang, Chun-Ying Lee, Tai-Hao Wen, Fu-Chun Chang, Shao-Ming Yu, Tung-Yin Lee, Meng-Fan Chang:
A 40-nm, 2M-Cell, 8b-Precision, Hybrid SLC-MLC PCM Computing-in-Memory Macro with 20.5 - 65.0TOPS/W for Tiny-Al Edge Devices. 1-3 - Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Mei-Chen Chuang, Rawan Naous, Chao-Kai Chuang, Takeshi Hashizume, Dar Sun, Chia-Fu Lee, Kerem Akarvardar, Saman Adham, Tan-Li Chou, Mahmut Ersin Sinangil, Yih Wang
A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations. 1-3 - Hyunsu Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Junyoung Song, Chulwoo Kim:
A 0.385-pJ/bit 10-Gb/s TIA-Terminated Di-Code Transceiver with Edge-Delayed Equalization, ECC, and Mismatch Calibration for HBM Interfaces. 1-3 - Tsung-Hsien Tsai, Ruey-Bin Sheen, Sheng-Yun Hsu, Ya-Tin Chang, Chih-Hsien Chang, Robert Bogdan Staszewski:
A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur. 1-3 - Diego Peña-Colaiocco
An Optimal Digital Beamformer for mm-Wave Phased Arrays with 660MHz Instantaneous Bandwidth in 28nm CMOS. 1-3 - Yi-Yen Hsieh, Yu-Cheng Lin, Chia-Hsiang Yang:
A 96.2nJ/class Neural Signal Processor with Adaptable Intelligence for Seizure Prediction. 1-3 - Kodai Ueyoshi, Ioannis A. Papistas, Pouya Houshmand, Giuseppe Maria Sarda
DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC. 1-3 - Seong Ju Lee, Kyu-Young Kim, Sanghoon Oh, Joonhong Park, Gimoon Hong, Dong Yoon Ka, Kyu-Dong Hwang, Jeongje Park, Kyeong Pil Kang, Jungyeon Kim, Junyeol Jeon, Nahsung Kim, Yongkee Kwon, Kornijcuk Vladimir, Woojae Shin, Jongsoon Won, Minkyu Lee, Hyunha Joo, Haerang Choi, Jaewook Lee, Donguc Ko, Younggun Jun, Keewon Cho, Ilwoong Kim, Choungki Song, Chunseok Jeong, Dae-Han Kwon, Jieun Jang, Il Park, Junhyun Chun, Joohwan Cho:
A 1ynm 1.25V 8Gb, 16Gb/s/pin GDDR6-based Accelerator-in-Memory supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep-Learning Applications. 1-3 - Li-Qun Weng, Li-De Chen, Hao-Chien Cheng, An-You Zheng, Kai-Ping Lin, Chao-Tsung Huang:
A HD 31fps 7×7-View Light-Field Factorization Processor for Dual-Layer 3D Factored Display. 1-3 - Ippei Akita
A 2.6mW 10pTI √ Hz 33kHz Magnetoimpedance-Based Magnetometer with Automatic Loop-Gain and Bandwidth Enhancement. 1-3 - Hyojun Kim
A 100MHz-Reference, 8GHz/16GHz, 177fsrms/223fsrms RO-Based IL-ADPLL Incorporating Reference Octupler with Probability-Based Fast Phase-Error Calibration. 1-3 - Gérard Billiot, Paul Mattei, Bogdan Vysotskyi, Adrien Reynaud
1024 3D-Stacked Monolithic NEMS Array with 375μm20.5mW 0.28ppm Frequency Deviation Pixel-level Readout for Zeptogram Gravimetric Sensing. 1-3 - Je-Min Hung, Yen-Hsiang Huang, Sheng-Po Huang, Fu-Chun Chang, Tai-Hao Wen, Chin-I Su, Win-San Khwa, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang:
An 8-Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory Macro using Time-Space-Readout with 1286.4-21.6TOPS/W for Edge-AI Devices. 1-3 - Yuhao Ju, Jie Gu:
A 65nm Systolic Neural CPU Processor for Combined Deep Learning and General-Purpose Computing with 95% PE Utilization, High Data Locality and Enhanced End-to-End Performance. 1-3 - Li Xu
A 210×340×50µm Integrated CMOS System f0r Micro-Robots with Energy Harvesting, Sensing, Processing, Communication and Actuation. 1-3 - Simone Mattia Dartizio, Francesco Buccoleri, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum
A 68.6fsrms-Total-integrated-Jitter and 1.5µs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching. 1-3 - David Joseph Munzer, Naga Sasikanth Mannem, Edgar Felipe Garay, Hua Wang:
A Broadband Mm-Wave VSWR-Resilient Joint True-Power Detector and Impedance Sensor Supporting Single-Ended Antenna Interfaces. 1-3 - Henry Hinton
A 200 x 256 Image Sensor Heterogeneously Integrating a 2D Nanomaterial-Based Photo-FET Array and CMOS Time-to-Digital Converters. 1-3 - Jiang Gong, Bishnu Patra, Luc Enthoven, Job van Staveren, Fabio Sebastiano, Masoud Babaie:
A 0.049mm2 7.1-to-16.8GHz Dual-Core Triple-Mode VCO Achieving 200dB FoMA in 22nm FinFET. 1-3 - Shuo Li, Xinjian Liu, Benton H. Calhoun:
A 32nA Fully Autonomous Multi-Input Single-Inductor Multi-Output Energy-Harvesting and Power-Management Platform with 1.2×105 Dynamic Range, Integrated MPPT, and Multi-Modal Cold Start-Up. 1-3 - Yang Wang, Yubin Qin, Dazheng Deng, Jingchuan Wei, Yang Zhou, Yuanqi Fan, Tianbao Chen, Hao Sun, Leibo Liu, Shaojun Wei, Shouyi Yin:
A 28nm 27.5TOPS/W Approximate-Computing-Based Transformer Processor with Asymptotic Sparsity Speculating and Out-of-Order Computing. 1-3 - Drew A. Hall
A CMOS Molecular Electronics Chip for Single-Molecule Biosensing. 1-3 - Dimin Niu, Shuangchen Li, Yuhao Wang, Wei Han, Zhe Zhang, Yijin Guan, Tianchan Guan, Fei Sun, Fei Xue, Lide Duan, Yuanwei Fang, Hongzhong Zheng, Xiping Jiang, Song Wang, Fengguo Zuo, Yubing Wang, Bing Yu, Qiwei Ren, Yuan Xie:
184QPS/W 64Mb/mm23D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System. 1-3 - Huajun Zhang
A 121.4dB DR, -109.8dB THD+N Capacitively-Coupled Chopper Class-D Audio Amplifier. 1-3 - Haozhe Zhu
COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning. 1-3 - Muya Chang, Samuel D. Spetalnick, Brian Crafton, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
A 40nm 60.64TOPS/W ECC-Capable Compute-in-Memory/Digital 2.25MB/768KB RRAM/SRAM System with Embedded Cortex M3 Microprocessor for Edge Recommendation Systems. 1-3 - Ping-Chun Wu, Jian-Wei Su
A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices. 1-3 - Harijot Singh Bindra, Jeroen Ponte, Bram Nauta
A 174μVRMS Input Noise, 1 G8/s Comparator in 22nm FDSOI with a Dynamic-Bias Preamplifier Using Tail Charge Pump and Capacitive Neutralization Across the Latch. 1-3 - Cameron Hill, James F. Buckwalter:
A 1-to-18GHz Distributed-Stacked-Complementary Triple-Balanced Passive Mixer With up to 33dBm IIP3 and Integrated LO Driver in 45nm CMOS SOI. 1-3 - Kazutoshi Hirose, Jaehoon Yu, Kota Ando, Yasuyuki Okoshi, Ángel López García-Arias
Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet. 1-3 - Sangwoo Kim
A Fully Digital Time-Mode CMOS Image Sensor with 22.9pJ/frame.pixel and 92dB Dynamic Range. 1-3 - Zhe Liu, Chirn Chye Boon, Chenyang Li, Kaituo Yang, Yangtao Dong, Ting Guo:
A 0.0078mm2 3.4mW Wideband Positive-feedback-Based Noise-Cancelling LNA in 28nm CMOS Exploiting Gm Boosting. 1-3 - Xinjian Liu, Sumanth Kamineni, Jacob Breiholz, Benton H. Calhoun, Shuo Li:
A 194nW Energy-Performance-Aware loT SoC Employing a 5.2nW 92.6% Peak Efficiency Power Management Unit for System Performance Scaling, Fast DVFS and Energy Minimization. 1-3 - Shoubhik Karmakar, Marco Berkhout, Kofi A. A. Makinwa, Qinwen Fan:
A -91 dB THD+N Resistor-Less Class-D Piezoelectric Speaker Driver Using a Dual Voltage/ Current Feedback for LC Resonance Damping. 1-3 - Kyu-Jin Choi
A Time-Division Multiplexed 8-Channel Non-Contact ECG Recording IC with a Common-Mode Interference Tolerance of 20VPP. 1-3 - Chuan-Yi Wu, Chi-Wei Liu, Jing-Siang Chen, Cong-Sheng Huang, Ting-Heng Lu, Ling-Chia Chen, I-Che Ou, Sook-Kuan Lee, Yen-Chi Chen, Po-Hung Chen, Chi-Te Liu, Ying-Chih Liao, Yu-Te Liao
A Self-powering Wireless Soil-pH and Electrical Conductance Monitoring IC with Hybrid Microbial Electrochemical and Photovoltaic Energy Harvesting. 1-3 - Changuk Lee, Byeongseol Kim, Jejung Kim, Sangwon Lee, Taejune Jeon, Woojun Choi, Sunggu Yang, Jong-Hyun Ahn
A Miniaturized Wireless Neural Implant with Body-Coupled Data Transmission and Power Delivery for Freely Behaving Animals. 1-3 - Ha-Il Song, Hanho Choi, Jun Young Yoo, Hyosup Won, Cheong Min Lee, Huxian Jin, Tai Young Kim, Woohyun Kwon
A 50Gb/s PAM-4 Bi-Directional Plastic Waveguide Link with Carrier Synchronization Using PI-Based Costas Loop. 1-3 - Chan Sam Park
A 145.2dB-DR Baseline-Tracking Impedance Plethysmogram IC for Neckband-Based Blood Pressure and Cardiovascular Monitoring. 1-3 - Bahram Zand, Mike Bichan, Alireza Mahmoodi, Mansour Shashaani, Jing Wang, Ruslana Shulyzki, James Guthrie, Katya Tyshchenko, Junhong Zhao, Eric Liu, Nima Soltani, Al Freeman, Rishi Anand, Syed Rubab, Ranjit Khela, Shaham Sharifian, Karl Herterich:
A 1-58.125Gb/s, 5-33dB IL Multi-Protocol Ethernet-Compliant Analog PAM-4 Receiver with 16 DFE Taps in 10nm. 1-3 - Lu Jie, Mingtao Zhan, Xiyuan Tang, Nan Sun:
A 0.014mm2 10kHz-BW Zoom-Incremental-Counting ADC Achieving 103dB SNDR and 100dB Full-Scale CMRR. 1-3 - Sungbong Park, Changkyu Lee, Sangcheon Park, Haeyong Park, Taeheon Lee, Dami Park, Minsung Heo, Inyong Park, Hyunyoung Yeo, Youna Lee, Juhee Lee, Beomsuk Lee, Dong-Chul Lee, Jinyoung Kim, Bokwon Kim, Jinsun Pyo, Shili Quan, Sungyong You, Inho Ro, Sungsoo Choi, SungIn Kim, Insung Joe, Jongeun Park, Chang-Hyo Koo, Jae-Ho Kim, Chong Kwang Chang, Taehee Kim, JinGyun Kim, Jamie Lee, Hyunchul Kim, Changrok Moon, Hyoung-Sub Kim:
A 64Mpixel CMOS Image Sensor with 0.50µm Unit Pixels Separated by Front Deep-Trench Isolation. 1-3 - Junyao Tang, Lei Zhao, Cheng Huang:
A 68.3% Efficiency Reconfigurable 400-/800-mW Capacitive Isolated DC-DC Converter with Common-Mode Transient Immunity and Fast Dynamic Response by Through-Power-Link Hysteretic Control. 1-3 - Jeong-Hyun Cho, Dong-Kyu Kim, Hong-Hyun Bae, Yong-Jin Lee, Seok-Tae Koh, Young-Hwan Choo, Ji-Seon Paek, Hyun-Sik Kim:
A 1.23W/mm2 83.7%-Efficiency 400MHz 6-Phase Fully Integrated Buck Converter in 28nm CMOS with On-Chip Capacitor Dynamic Re-Allocation for Inter-Inductor Current Balancing and Fast DVS of 75mV/ns. 1-3 - Jingyi Yuan, Zeguo Liu, Feng Wu, Lin Cheng:
A 12V/24V-to-1V DSD Power Converter with 56mV Droop and 0.9µS 1% Settling Time for a 3A/20ns Load Transient. 1-3 - Ted Pekny, Luyen Vu, Jeff Tsai, Dheeraj Srinivasan, Erwin Yu, Jonathan Pabustan, Joe Xu, Srinivas Deshmukh, Kim-Fung Chan, Michael Piccardi, Kevin Xu, Guan Wang, Kaveh Shakeri, Vipul Patel, Tomoko Iwasaki, Tongji Wang, Padma Musunuri, Carl Gu, Ali Mohammadzadeh, Ali Ghalam, Violante Moschiano, Tommaso Vali, Jae-Kwan Park, June Lee, Ramin Ghodsi:
A 1-Tb Density 4b/Cell 3D-NAND Flash on 176-Tier Technology with 4-Independent Planes for Read using CMOS-Under-the-Array. 1-3 - Jaeyoung Seo, Sooeun Lee, Myungguk Lee, Changjae Moon, Byungsub Kim:
A 20-Gb/s/pin 0.0024-mm2 Single-Ended DECS TRX with CDR-less Self-Slicing/Auto-Deserialization to Improve Tolerance on Duty Cycle Error and RX Supply Noise for DCC/CDR-less Short-Reach Memory Interfaces. 1-3 - Kwantae Kim
A 23μW Solar-Powered Keyword-Spotting ASIC with Ring-Oscillator-Based Time-Domain Feature Extraction. 1-3 - Chen Chen, Jin Liu, Hoi Lee:
A 2-5MHz Multiple DC Output Hybrid Boost Converter with Scalable CR Boosting Scheme Achievi 1 ng 91% Efficie 1 ncy at a Conversion Ratio of 12. 1-3 - Raghavan Kumar, Vikram B. Suresh, Mark A. Anders, Steven K. Hsu, Amit Agarwal, Vivek K. De, Sanu K. Mathew:
An 8.3-to-18Gbps Reconfigurable SCA-Resistant/Dual-Core/Blind-Bulk AES Engine in Intel 4 CMOS. 1-3 - Onur Memioglu, Yu Zhao, Behzad Razavi:
A 300GHz 52mW CMOS Receiver with On-Chip LO Generation. 1-3 - George Zettles, Scott Willenborg, Blake R. Johnson, Andrew Wack, Brian Allison:
26.2 Design Considerations for Superconducting Quantum Systems. 1-3 - Thomas Burd, Wilson Li, James Pistole, Srividhya Venkataraman, Michael McCabe, Timothy Johnson, James Vinh, Thomas Yiu, Mark Wasio, Hon-Hin Wong, Daryl Lieu, Jonathan White, Benjamin Munger, Joshua Lindner, Javin Olson, Steven Bakke, Jeshuah Sniderman, Carson Henrion, Russell Schreiber, Eric Busta, Brett Johnson, Tim Jackson, Aron Miller, Ryan Miller, Matthew Pickett, Aaron Horiuchi, Josef Dvorak, Sabeesh Balagangadharan, Sajeesh Ammikkallingal, Pankaj Kumar:
Zen3: The AMD 2nd-Generation 7nm x86-64 Microprocessor Core. 1-3 - Sam Razavian
A Highly Power Efficient 2×3 PIN-Diode-Based Intercoupled THz Radiating Array at 425GHz with 18.1dBm EIRP in 90nm SiGe BiCMOS. 1-3 - Luya Zhang
A 480-Multiplication-Factor 13.2-to-17.3GHz Sub-Sampling PLL Achieving 6.6mW Power and -248.1 dB FoM Using a Proportionally Divided Charge Pump. 1-3 - Charlotte Frenkel, Giacomo Indiveri:
ReckOn: A 28nm Sub-mm2 Task-Agnostic Spiking Recurrent Neural Network Processor Enabling On-Chip Learning over Second-Long Timescales. 1-3 - Fengbin Tu, Yiqi Wang, Zihan Wu, Ling Liang, Yufei Ding, Bongjin Kim, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin:
A 28nm 29.2TFLOPS/W BF16 and 36.5TOPS/W INT8 Reconfigurable Digital CIM Processor with Unified FP/INT Pipeline and Bitwise In-Memory Booth Multiplication for Cloud Deep Learning Acceleration. 1-3 - Christopher Schaef, Tamir Salus, Rachid Rayess, Siddarth Kulasekaran, Mat Manusharow, Kaladhar Radhakrishnan, Jonathan Douglas:
A IMax |max, Fully Integrated Multi-Phase Voltage Regulator with 91.5% Peak Efficiency at 1.8 to 1V, Operating at 50MHz and Featuring a Digitally Assisted Controller with Automatic Phase Shedding and Soft Switching in 4nm Class FinFET CMOS. 1-3 - Jun-Suk Bang, Dong-Su Kim, Jeongkwang Lee, Sung-Youb Jung, Young-Hwan Choo, Seungchan Park, Young-Ho Jung, Jae-Young Ko, Takahiro Norniyama, Jongbeom Baek, Jae-Yeol Han, Sang-Han Lee, Ik-Hwan Kim, Ji-Seon Paek, Jongwoo Lee, Thomas Byunghak Cho:
2-Tx Digital Envelope-Tracking Supply Modulator Achieving 200MHz Channel Bandwidth and 93.6% Efficiency for 2G/3G/LTE/NR RF Power Amplifiers. 1-3 - Youngwoo Ji, Jiawei Liao, Sina Arjmandpour
A Second-Order Temperature-Compensated On-Chip R-RC Oscillator Achieving 7.93ppm/°C and 3.3pJ/Hz in -40°C to 125°C Temperature Range. 1-3 - Yu Zhao, Onur Memioglu, Behzad Razavi:
A 56GHz 23mW Fractional-N PLL with 110fs Jitter. 1-3 - Yeonwook Jung, Seongseop Lee, Hyojun Kim, SeongHwan Cho:
A Supply-Noise-Induced Jitter-Cancelling Clock Distribution Network for LPDDR5 Mobile DRAM featuring a 2nd-order Adaptive Filter. 1-3 - Ashutosh Verma, Venumadhav Bhagavatula, Amitoj Singh, Wanghua Wu, Hariharan Nagarajan, Pak-Kim Lau, Xiaohua Yu, Omar Elsayed, Ajaypat Jain, Anirban Sarkar, Fan Zhang, Che-Chun Kuo, Patrick McElwee, Pei-Yuan Chiang, Chengkai Guo, Zhanjun Bai, Tienyu Chang, Abishek Mann, Andreas Rydin, Xingliang Zhao, Jeiyoung Lee, Daeyoung Yoon, Chih-Wei Yao, Siuchuang-Ivan Lu, Sang Won Son, Thomas Byunghak Cho:
A 16-Channel, 28/39GHz Dual-Polarized 5G FR2 Phased-Array Transceiver IC with a Quad-Stream IF Transceiver Supporting Non-Contiguous Carrier Aggregation up to 1.6GHz BW. 1-3 - Christoph Rindfleisch, Bernhard Wicht:
A 110V/230V 0.3W Offline Chip-Scale Power Supply with Integrated Active Zero-Crossing Buffer and Voltage-Interval-Based Dual-Mode Control. 1-3 - Arthur Campos de Oliveira, Sining Pan, Kofi A. A. Makinwa:
A MEMS Coriolis-Based Mass-Flow-to-Digital Converter with 100µg/h/√Hz Noise i Floor and Zero Stability of ±0.35mg/h. 1-3 - Qiang Fang, Longyang Lin, Yao Zu Wong, Hui Zhang
Side-Channel Attack Counteraction via Machine Learning-Targeted Power Compensation for Post-Silicon HW Security Patching. 1-3 - Feifei Chen, Ka-Fai Un
A 108nW 0.8mm2 Analog Voice Activity Detector (VAD) Featuring a Time-Domain CNN as a Programmable Feature Extractor and a Sparsity-Aware Computational Scheme in 28nm CMOS. 1-3 - Amit Kumar Mishra
A 9b-Linear 14GHz Integrating-Mode Phase Interpolator in 5nm FinFET Process. 1-3 - Aart De Geus:
Catalyzing the Impossible: Silicon, Software, and Smarts for the SysMoore Era. 10-16 - Marco Cassis:
Intelligent Sensing: Enabling the Next "Automation Age". 17-24 - Inyup Kang:
The Art of Scaling: Distributed and Connected to Sustain the Golden Age of Computation. 25-31 - Renee James:
The Future of the High-Performance Semiconductor Industry and Design. 32-35 - Wilfred Gomes, Altug Koker, Patrick N. Stover, Doug B. Ingerly, Scott Siers, Srikrishnan Venkataraman, Chris Pelto, Tejas Shah, Amreesh Rao, Frank O'Mahony, Eric Karl, Lance Cheney, Iqbal Rajwani, Hemant Jain, Ryan Cortez, Arun Chandrasekhar, Basavaraj Kanthi, Raja Koduri:
Ponte Vecchio: A Multi-Tile 3D Stacked Processor for Exascale Computing. 42-44 - Nevine Nassif, Ashley O. Munch, Carleton L. Molnar, Gerald Pasdast, Sitaraman V. Lyer, Zibing Yang, Oscar Mendoza, Mark Huddart, Srikrishnan Venkataraman, Sireesha Kandula, Rafi Marom, Alexandra M. Kern, William J. Bowhill, David R. Mulvihill, Srikanth Nimmagadda, Varma Kalidindi, Jonathan Krause, Mohammad M. Haq, Roopali Sharma, Kevin Duda:
Sapphire Rapids: The Next-Generation Intel Xeon Scalable Processor. 44-46 - Ofer Geva, Christopher J. Berry, Robert J. Sonnelitter, David Wolpert, Adam Collura, Thomas Strach, Di Phan, Cédric Lichtenau, Alper Buyuktosunoglu, Hubert Harrer, Jeffrey A. Zitz, Chad Marquart, Douglas Malone, Tobias Webel, Adam Jatkowski, John Isakson, Dina Hamid, Mark Cichanowski, Michael Romain, Faisal Hasan, Kevin Williams, Jesse Surprise, Chris Cavitt, Mark Cohen:
IBM Telum: a 16-Core 5+ GHz DCM. 46-48 - Rahul M. Rao, Christopher J. Gonzalez, Eric Fluhr, Abraham Mathews, Andrew Bianchi, Daniel Dreps, David Wolpert, Eric Lai, Gerald Strevig, Glen A. Wiedemeier, Philipp Salz, Ryan Kruse:
POWER10™: A 16-Core SMT8 Server Processor With 2TB/s Off-Chip Bandwidth in 7nm Technology. 48-50 - Ashish Nayak, HsinChen Chen, Hugh Mair, Rolf Lagerquist, Tao Chen, Anand Rajagopalan, Gordon Gammie, Ramu Madhavaram, Madhur Jagota, C. J. Chung, Jenny Wiedemeier, Bala Meera, Chao-Yang Yeh, Maverick Lin, Curtis Lin, Vincent Lin, Jiun Lin, Y. S. Chen, Barry Chen, Cheng-Yuh Wu, Ryan ChangChien, Ray Tzeng, Kelvin Yang, Achuta Thippana, Ericbill Wang, Shih-Arn Hwang:
A 5nm 3.4GHz Tri-Gear ARMv9 CPU Subsystem in a Fully Integrated 5G Flagship Mobile SoC. 50-52 - Uneeb Rathore, Sumeet Singh Nagi, Subramanian S. Iyer, Dejan Markovic:
A 16nm 785GMACs/J 784-Core Digital Signal Processor Array With a Multilayer Switch Box Interconnect, Assembled as a 2×2 Dielet with 10μm-Pitch Inter-Dielet I/O for Runtime Multi-Program Reconfiguration. 52-54 - Jaehong Jung
A Single-Crystal-Oscillator-Based Clock-Management IC with 18× Start-Up Time Reduction and 0.68ppm/ºC Duty-Cycled Machine-Learning-Based RCO Calibration. 58-60 - Jaehong Jung
A 52MHz -158.2dBc/Hz PN @ 100kHz Digitally Controlled Crystal Oscillator Utilizing a Capacitive-Load-Dependent Dynamic Feedback Resistor in 28nm CMOS. 60-62 - Zhong Tang, Roger Zarnparette, Yoshikazu Furuta, Tomohiro Nezuka, Kofi A. A. Makinwa:
A ±25A Versatile Shunt-Based Current Sensor with 10kHz Bandwidth and ±0.25% Gain Error from -40°C to 85°C Using 2-Current Calibration. 66-68 - Bo Wang
A BJT-Based CMOS Temperature Sensor Achieving an Inaccuracy of ±0.45°C(3σ) from °50°C to 180°C and a Resolution-FoM of 7.2pJ.K2 at 150°C. 72-74 - Mohamed Elkhouly, Jaegeun Ha, Michael J. Holyoak, David Hendry, Mustafa Sayginer, Ryan Enright, Ioannis Kimionis
Fully Integrated 2D Scalable TX/RX Chipset for D-Band Phased-Array-on-Glass Modules. 76-78 - Steven Callender, Amy Whitcombe, Abhishek Agrawal, Ritesh Bhat, Mustafijur Rahman, Chun C. Lee, Peter Sagazio, Georgios C. Dogiamis, Brent R. Carlton, Mark Chakravorti, Stefano Pellerano, Christopher D. Hull:
A Fully Integrated 160Gb/s D-Band Transmitter with 1.1 pJ/b Efficiency in 22nm FinFET Technology. 78-80 - Xibi Chen, Muhammad Ibrahim Wasiq Khan, Xiang Yi, Xingcun Li
A 140GHz Transceiver with Integrated Antenna, Inherent-Low-Loss Duplexing and Adaptive Self-Interference Cancellation for FMCW Monostatic Radar. 80-82 - Linghan Zhang, Masoud Babaie:
A 23-to-29GHz Receiver with mm-Wave N-Input-N-Output Spatial Notch Filtering and Autonomous Notch-Steering Achieving 20-to-40dB mm-Wave Spatial Rejection and -14dBm In-Notch IP1 dB. 82-84 - Xi Fu
A 3.4mW/element Radiation-Hardened Ka-Band CMOS Phased-Array Receiver Utilizing Magnetic-Tuning Phase Shifter for Small Satellite Constellation. 90-92 - Yasuharu Ota, Kazuhiro Morimoto, Tomoya Sasago, Mahito Shinohara, Yukihiro Kuroda, Wataru Endo, Yu Maehashi, Shintaro Maekawa, Hiroyuki Tsuchiya, Aymantarek Abdelahafar, Shingo Hikosaka, Masanao Motoyama, Kenzo Tojima, Kosei Uehira, Junji Iwata, Fumihiro Inui, Yasushi Matsuno, Katsuhito Sakurai, Takeshi Ichikawa:
A 0.37W 143dB-Dynamic-Range 1Mpixel Backside-Illuminated Charge-Focusing SPAD Image Sensor with Pixel-Wise Exposure Control and Adaptive Clocked Recharging. 94-96 - Enrico Manuzzato, Alessandro Tontini, Andrej Seljak, Matteo Perenzoni:
A 64×64-Pixel Flash LiDAR SPAD Imager with Distributed Pixel-to-Pixel Correlation for Background Rejection, Tunable Automatic Pixel Sensitivity and First-Last Event Detection Strategies for Space Applications. 96-98 - Seonghyeok Park
An 80×60 Flash LiDAR Sensor with In-Pixel Histogramming TDC Based on Quaternary Search and Time-Gated Δ-Intensity Phase Detection for 45m Detectable Range and Background Light Cancellation. 98-100 - Keita Yasutomi, Tatsuki Furuhashi, Koki Sagawa, Taishi Takasawa, Keiichiro Kagawa, Shoji Kawahito:
A 38µm Range Precision Time-of-Flight CMOS Range Line Imager with Gating Driver Jitter Reduction Using Charge-Injection Pseudo Photocurrent Reference. 100-102 - Taesub Jung, Masato Fujita, Jeongjin Cho, Kyungduck Lee, Doosik Seol, Sungmin An, Chanhee Lee, Youjin Jeong, Minji Jung, Sachoun Park, Seungki Baek, Seungki Jung, Seunghwan Lee, Jungbin Yun, Eun Sub Shim, Heetak Han, Eunkyung Park, Haesick Sul, Sehyeon Kang, Kyungho Lee, JungChak Ahn, Duckhyun Chang:
A 1/1.57-inch 50Mpixel CMOS Image Sensor With 1.0μm All-Directional Dual Pixel by 0.5μm-Pitch Full-Depth Deep-Trench Isolation Technology. 102-104 - Hirotaka Murakami, Eric Bohannon, John Childs, Grace Gui, Eric Moule, Katsuhiko Hanzawa, Tomofumi Koda, Chiaki Takano, Toshimasa Shimizu, Yuki Takizawa, Adarsh Basavalingappa, Robert Childs, Cody Cziesler, Robert Jarnot, Kazumasa Nishimura, Scott Rogerson, Yoshikazu Nitta:
A 4.9Mpixel Programmable-Resolution Multi-Purpose CMOS Image Sensor for Computer Vision. 104-106 - Xu Yang, Linhu Zhao, Menglian Zhao, Zhichao Tan, Lenian He, Yong Ding, Wuhua Li, Wanyuan Qu:
A 5V Input 98.4% Peak Efficiency Reconfigurable Capacitive-Sigma Converter With Greater than 90% Peak Efficiency for the Entire 0.4~1.2V Output Range. 108-110 - Gyu-Wan Lim, Gyeong-Gu Kang, Hyunggun Ma, Moonjae Jeong, Hyun-Sik Kim:
A 10b Source-Driver IC with LSB-Stacked LV-to-HV-Amplify DAC Achieving 2688μm2/channel and 4.8mV DVO for Mobile OLED Displays. 110-112 - Yoav Segal, Amir Laufer, Ahmad Khairi, Yoel Krupnik, Marco Cusmai, Itamar Levin, Ari Gordon, Yaniv Saban, Vitali Rahinskj, Gadi Ori, Noam Familia, Stas Litski, Tali Warshavsky, Udi Virobnik, Yeshayahu Horwitz, Ajay Balankutty, Shiva Kiran, Samuel Palermo
A 1.41pJ/b 224Gb/s PAM-4 SerDes Receiver with 31dB Loss Compensation. 114-116 - Zhendong Guo, Ahmed Mostafa, A. Elshazly, Bo Chen, B. Wang, C. Han, Chenkun Wang, D. Zhou, Davide Visani, Edmund Hsiao, F. Chu, Fei Lu, G. Cui, H. Zhang, H. Wang, H. Zhao, J. Lin, J. Gu, L. Luo, L. Jiang, M. Singh, M. Gambhir, Mehedi Hasan, M. Wu, M. J. Yoo, P. Liu, S. Kollu, T. Ye, X. Zhao, X. Yang, X. Han, Y. Huang, Y. Sun, Z. Yu, Z. H. Jiang, Z. Adal, Z. Yan:
A 112.5Gb/s ADC-DSP-Based PAM-4 Long-Reach Transceiver with >50dB Channel Loss in 5nm FinFET. 116-118 - Bingyi Ye, Kai Sheng
A 2.29pJ/b 112Gb/s Wireline Transceiver with RX 4-Tap FFE for Medium-Reach Applications in 28nm CMOS. 118-120 - Namik Kocaman, Ullas Singh, Bharath Raghavan, Arvindh Iyer, Kumar Thasari, Saurabh Surana, Jun Won Jung, Jaehun Jeong, Heng Zhang, Anand Vasani, Yonghyun Shim, Zhi Huang, Adesh Garg, Hsiang-bin Lee, Bo Wu, Feifei Liu, Ray Wang, Matthew Loh, Alex Wang, Mario Caresosa, Bo Zhang, Afshin Momtaz:
An 182mW 1-60Gb/s Configurable PAM-4/NRZ Transceiver for Large Scale ASIC Integration in 7nm FinFET Technology. 120-122 - Gautam Reddy Gangasani, D. Hanson, Daniel W. Storaska, H. H. Xu, M. Kelly, M. Shannon, Michael Sorna, Michael Wielgos, P. B. Ramakrishna, S. Shi, S. Parker, U. K. Shukla, W. Kelly, W. Su, Z. Yu:
A 1.6Tb/s Chiplet over XSR-MCM Channels using 113Gb/s PAM-4 Transceiver with Dynamic Receiver-Driven Adaptation of TX-FFE and Programmable Roaming Taps in 5nm CMOS. 122-124 - Jong Yuh, Jason Li, Heguang Li, Yoshihiro Oyama, Cynthia Hsu, Pradeep Anantula, Stanley Jeong, Anirudh Amarnath, Siddhesh Darne, Sneha Bhatia, Tianyu Tang, Aditya Arya, Naman Rastogi, Naoki Ookuma, Hiroyuki Mizukoshi, Alex Yap, Demin Wang, Steve Kim, Yonggang Wu, Min Peng, Jason Lu, Tommy Ip, Seema Malhotra, David Han, Masatoshi Okumura, Jiwen Liu, John Sohn, Hardwell Chibvongodze, Muralikrishna Balaga, Aki Matsuda, Chakshu Puri, Chen Chen, Indra K. V, Chaitanya G, Venky Ramachandra, Yosuke Kato, Ravi Kumar, Huijuan Wang, Farookh Moogat, In-Soo Yoon, Kazushige Kanda, Takahiro Shimizu, Noboru Shibata, Takashi Shigeoka, Kosuke Yanagidaira, Takuyo Kodama, Ryo Fukuda, Yasuhiro Hirashima, Mitsuhiro Abe:
A 1-Tb 4b/Cell 4-Plane 162-Layer 3D Flash Memory With a 2.4-Gb/s I/O Speed Interface. 130-132 - Wanik Cho, Jongseok Jung, Jongwoo Kim, Junghoon Nam, Sangkyu Lee, Yujong Noh, Dauni Kim, Wanseob Lee, Kayoung Cho, Kwanho Kim, Heejoo Lee, Sooyeol Chai, Eunwoo Jo, Hanna Cho, Jong-Seok Kim
A 1-Tb, 4b/Cell, 176-Stacked-WL 3D-NAND Flash Memory with Improved Read Latency and a 14.8Gb/mm2 Density. 134-135 - Moosung Kim, Sung-Won Yun, Jungjune Park, Hyun Kook Park, Jungyu Lee, Yeong Seon Kim, Dae-Hoon Na, Sara Choi, Youngsun Song, Jonghoon Lee, Hyun-Jun Yoon, Kangbin Lee, Byunghoon Jeong, Sanglok Kim, Junhong Park, Cheon An Lee, Jaeyun Lee, Ji-Sang Lee, Jin Young Chun, Joonsuc Jang, Younghwi Yang, Seung Hyun Moon, Myung-Hoon Choi, Wontae Kim, Jungsoo Kim, Seok-Min Yoon, Pansuk Kwak, Myunghun Lee, Raehyun Song, Sunghoon Kim, Chiweon Yoon, Dongku Kang, Jin-Yub Lee, Jai Hyuk Song:
A 1Tb 3b/Cell 8th-Generation 3D-NAND Flash Memory with 164MB/s Write Throughput and a 2.4Gb/s Interface. 136-137 - Han-Wen Hu
A 512Gb In-Memory-Computing 3D-NAND Flash Supporting Similar-Vector-Matching Operations on Edge-AI Devices. 138-140 - Somnath Kundu, Timo Huusari, Hao Luo, Abhishek Agrawal, Eduardo Alban, Sarah Shahraini, Thao Xiong, Dan Lake, Stefano Pellerano, Jason Mix, Nasser A. Kurd, Mohamed Abdel-moneum, Brent R. Carlton:
A 2-to-2.48GHz Voltage-Interpolator-Based Fractional-N Type-I Sampling PLL in 22nm FinFET Assisting Fast Crystal Startup. 144-146 - Hyman Shanan, Declan Dalton, Vamshi Chillara, Pablo Dato:
A 9-to-12GHz Coupled-RTWO FMCW ADPLL with 97fs RMS Jitter, -120dBc/Hz PN at 1MHz Offset, and With Retrace Time of 12.5ns and 2μs Chirp Settling Time. 146-148 - Haikun Jia, Ruichang Ma, Wei Deng, Zhihua Wang, Baoyong Chi:
A 53.6-to-60.2GHz Many-Core Fundamental Oscillator With Scalable Mesh Topology Achieving -136.0dBc/Hz Phase Noise at 10MHz Offset and 190.3dBc/Hz Peak FoM in 65nm CMOS. 154-156 - Juzheng Liu, Mohsen Hassanpourghadi, Mike Shuo-Wei Chen:
A 10GS/s 8b 25fJ/c-s 2850um2 Two-Step Time-Domain ADC Using Delay-Tracking Pipelined-SAR TDC with 500fs Time Step in 14nm CMOS Technology. 160-162 - Jia-Ching Wang, Tai-Haur Kuo:
A 0.82mW 14b 130MS/S Pipelined-SAR ADC With a Distributed Averaging Correlated Level Shifting (DACLS) Ringamp and Bypass-Window Backend. 162-164 - Mingtao Zhan, Lu Jie, Xiyuan Tang, Nan Sun:
A 0.004mm2 200MS/S Pipelined SAR ADC with kT/C Noise Cancellation and Robust Ring-Amp. 164-166 - Jesper Steensgaard, Richard Reay, Raymond Perry, Dave Thomas, Geoffrey Tu, George Reitsma:
A 24b 2MS/s SAR ADC with 0.03ppm INL and 106.3dB DR in 180nm CMOS. 168-170 - Yu-Yan Liu, Menglian Zhao, Yibo Zhao, Xiaopeng Yu, Nianxiong Nick Tan, Le Ye, Zhichao Tan:
A 4.96µW 15b Self-Timed Dynamic-Amplifier-Based Incremental Zoom ADC. 170-172 - Yen-Cheng Chiu, Chia-Sheng Yang, Shih-Hsih Teng, Hsiao-Yu Huang, Fu-Chun Chang, Yuan Wu, Yu-An Chien, Fang-Ling Hsieh, Chung-Yuan Li, Guan-Yi Lin, Po-Jung Chen, Tsen-Hsiang Pan, Chung-Chuan Lo, Win-San Khwa, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Chieh-Pu Lo, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang:
A 22nm 4Mb STT-MRAM Data-Encrypted Near-Memory Computation Macro with a 192GB/s Read-and-Decryption Bandwidth and 25.1-55.1TOPS/W 8b MAC for AI Operations. 178-180 - Yihan Zhang
Single-Mode CMOS 6T-SRAM Macros With Keeper-Loading-Free Peripherals and Row-Separate Dynamic Body Bias Achieving 2.53fW/bit Leakage for AIoT Sensing Platforms. 184-186 - Bonan Yan, Jeng-Long Hsu, Pang-Cheng Yu, Chia-Chi Lee, Yaojun Zhang, Wenshuo Yue, Guoqiang Mei, Yuchao Yang, Yue Yang, Hai Li, Yiran Chen, Ru Huang:
A 1.041-Mb/mm2 27.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications. 188-190 - Xiaohua Huang, Horacio Londoño-Ramírez
A 256-Channel Actively-Multiplexed µECoG Implant with Column-Parallel Incremental ΔΣ ADCs Employing Bulk-DACs in 22-nm FDSOI Technology. 200-202 - Adam Y. Wang
A CMOS Cellular Interface Array for Digital Physiology Featuring High-Density Multi-Modal Pixels and Reconfigurable Sampling Rate. 202-204 - Dokyung Lim, Sounghun Shin, Seungmin Lee, Kihyun Kwon, Jeongmin An, Wonsik Yu, Chanyoung Jeong, WooSeok Kim, Michael Choi, Jongshin Shin:
Clock Generator with IS026262 ASIL-D Grade Safety Mechanism for SoC Clocking Application. 210-212 - Rongjin Xu, Dawei Ye, Sirou Li, Chuanjin Richard Shi:
A 0.021mm2 65nm CMOS 2.5GHz Digital Injection-Locked Clock Multiplier with Injection Pulse Shaping Achieving -79dBc Reference Spur and 0.496mW/GHz Power Efficiency. 214-216 - Jae-Gon Lee
Fully Automated Hardware-Driven Clock-Gating Architecture with Complete Clock Coverage for 5nm Exynos Mobile SoC. 216-218 - Junghyun Park, Jooseong Kim, Kwangho Kim, Jun-Hyeok Yang, Michael Choi, Jongshin Shin:
A 0.65V 1316µm2Fully Synthesizable Digital Temperature Sensor Using Wire Metal Achieving O.16nJ.%2-Accuracy FoM in 5nm FinFET CMOS. 220-222 - Chi-Hsiang Huang, Arindam Mandal, Diego Peña-Colaiocco
Energy Minimization of Duty-Cycled Systems Through Optimal Stored-Energy Recycling from Idle Domains. 222-224 - Yu-Yung Kao, Tz-Wun Wang
A Monolithic GaN-Based Driver and GaN Power HEMT with Diode-Emulated GaN Technique for 50MHz Operation and Sub-0.2ns Deadtime Control. 228-230 - Chen Chen, Jin Liu, Hoi Lee:
A 2.5-5MHz 87% Peak Efficiency 48V-to-1V Integrated Hybrid DC-DC Converter Adopting Ladder SC Network with Capacitor-Assisted Dual-Inductor Filtering. 234-236 - Dongfang Pan
A 1.2W 51%-Peak-Efficiency Isolated DC-DC Converter with a Cross-Coupled Shoot-Through-Free Class-D Oscillator Meeting the CISPR-32 Class-B EMI Standard. 240-242 - Jun-Seok Park, Changsoo Park, Suknam Kwon, Hyeong-Seok Kim, Taeho Jeon, Yesung Kang, Heonsoo Lee, Dongwoo Lee
A Multi-Mode 8K-MAC HW-Utilization-Aware Neural Processing Unit with a Unified Multi-Precision Datapath in 4nm Flagship Mobile SoC. 246-248 - Jin-O. Seo
ARCHON: A 332.7TOPS/W 5b Variation-Tolerant Analog CNN Processor Featuring Analog Neuronal Computation Unit and Analog Memory. 258-260 - Laura Fick, Skylar Skrzyniarz, Malav Parikh, Michael B. Henry, David Fick:
Analog Matrix Processor for Edge AI Real-Time Video Analytics. 260-262 - Dewei Wang, Chuan-Tung Lin, Gregory K. Chen, Phil C. Knag, Ram Kumar Krishnamurthy, Mingoo Seok:
DIMC: 2219TOPS/W 2569F2/b Digital In-Memory Computing Macro in 28nm Based on Approximate Arithmetic Hardware. 266-268 - Hikmet Çeliker
Flex6502: A Flexible 8b Microprocessor in 0.8µm Metal-Oxide Thin-Film Transistor Technology Implemented with a Complete Digital Design Flow Running Complex Assembly Code. 272-274 - Baibhab Chatterjee
A 65nm 63.3µW 15Mbps Transceiver with Switched-Capacitor Adiabatic Signaling and Combinatorial-Pulse-Position Modulation for Body-Worn Video-Sensing AR Nodes. 276-278 - Kai Sheng
A 4.6pJ/b 200Gb/s Analog DP-QPSK Coherent Optical Receiver in 28nm CMOS. 282-284 - Arian Hashemi Talkhooncheh, Weiwei Zhang
A 2.4pJ/b 100Gb/s 3D-integrated PAM-4 Optical Transmitter with Segmented SiP MOSCAP Modulators and a 2-Channel 28nm CMOS Driver. 284-286 - Jinglin Xu, Ruida Yun, Baoxing Chen:
A 10Gb/s Digital Isolator Using Coupled Split-Ring Resonators with 24kVpk Surge Capability and 100kV/μS Common-Mode Transient Immunity. 286-288 - Zhaowen Wang
A 65nm CMOS, 3.5-to-11GHz, Less-Than-1.45LSB-INLpp, 7b Twin Phase Interpolator with a Wideband, Low-Noise Delta Quadrature Delay-Locked Loop for High-Speed Data Links. 292-294 - Prescott H. McLaughlin, Kishalay Datta, Jason T. Stauth
A Monolithic 3: 1 Resonant Dickson Converter with Variable Regulation and Magnetic-Based Zero-Current Detection and Autotuning. 304-306 - Guigang Cai, Yan Lu, Rui Paulo Martins:
A Battery-Input Sub-1V Output 92.9% Peak Efficiency 0.3A/mm2 Current Density Hybrid SC-Parallel-Inductor Buck Converter with Reduced Inductor Current in 65nm CMOS. 312-314 - Xingcun Li
A 110-to-130GHz SiGe BiCMOS Doherty Power Amplifier With Slotline-Based Power-Combining Technique Achieving >22dBm Saturated Output Power and >10% Power Back-off Efficiency. 316-318 - Wei Zhu, Jiawen Wang, Ruitao Wang
A 1V 32.1 dBm 92-to-102GHz Power Amplifier with a Scalable 128-to-1 Power Combiner Achieving 15% Peak PAE in a 65nm Bulk CMOS Process. 318-320 - Zonglin Ma, Kaixue Ma, Keping Wang, Fanyi Meng:
A 28GHz Compact 3-Way Transformer-Based Parallel-Series Doherty Power Amplifier With 20.4%/14.2% PAE at 6-/12-dB Power Back-off and 25.5dBm PSAT in 55nm Bulk CMOS. 320-322 - Jeongsoo Park
A 26-to-39GHz Broadband Ultra-Compact High-Linearity Switchless Hybrid N/PMOS Bi-Directional PA/LNA Front-End for Multi-Band 5G Large-Scaled MIMO System. 322-324 - Bassam Khamaisi, David Ben-Haim, Anna Nazimov, Assaf Ben Bassat, Shahar Gross, N. Shay, G. Asa, V. Spector, Yishai Eilat, A. Azam, Eli Borokhovich, I. Shternberg, Phillip Skliar, Elad Solomon, A. Beidas, T. A. Hazira, Aaron Lane, Eyal Shaviv, G. Nudelman, E. Dahan, M. S. Shemer, Nahum Kimiagarov, Ashoke Ravi, Ofir Degani:
A 16nm, +28dBm Dual-Band All-Digital Polar Transmitter Based on 4-core Digital PA for Wi-Fi6E Applications. 324-326 - Qinjing Pan, Tianxiang Qu
A 0.5mΩ/√Hz 106dB SNR 0.45cm2 Dry-Electrode Bioimpedance Interface with Current Mismatch Cancellation and Boosted Input Impedance of 100MΩ at 50kHz. 332-334 - Sehwan Lee, Yoonsung Choi, Geunha Kim, Seungyeob Baik, Taeryoung Seol
A 0.7V 17fJ/Step-FOMW 178.1dB-FOMSNDR 10kHz-BW 560mVPP True-ExG Biopotential Acquisition System with Parasitic-Insensitive 421MΩ Input Impedance in 0.18μm CMOS. 336-338 - Uisub Shin, Laxmeesha Somappa, Cong Ding, Yashwanth Vyza, Bingzhao Zhu, Alix Trouillet
A 256-Channel 0.227µJ/class Versatile Brain Activity Classification and Closed-Loop Neuromodulation SoC with 0.004mm2-1.51 µW/channel Fast-Settling Highly Multiplexed Mixed-Signal Front-End. 338-340 - Ji-Hyoung Cha, Jee-Ho Park
A Reconfigurable Sub-Array Multiplexing Microelectrode Array System With 24, 320 Electrodes and 380 Readout Channels for Investigating Neural Communication. 342-344 - Sina Faraji Alamouti, Cem Yalcin, Jasmine Jan
An SpO2 Sensor Using Reconstruction-Free Sparse Sampling for 70% System Power Reduction. 344-346 - Raghu Prabhakar, Sumti Jairath, Jinuk Luke Shin:
SambaNova SN10 RDU: A 7nm Dataflow Architecture to Accelerate Software 2.0. 350-352 - Shuji Yamamura, Yasunobu Akizuki, Hideyuki Sekiguchi, Takumi Maruyama, Tsutomu Sano, Hiroyuki Miyazaki, Toshio Yoshida:
A64FX: 52-Core Processor Designed for the 442PetaFLOPS Supercomputer Fugaku. 352-354 - Vikram B. Suresh, Chandra S. Katta, Srinivasan Rajagopalan, Tao Z. Zhou, Amit Kumar Patel, Raju Rakha, Nikhil Krishna Gopalakrishna, Sanu Mathew, Ajat Hukkoo:
Bonanza Mine: an Ultra-Low-Voltage Energy-Efficient Bitcoin Mining ASIC. 354-356 - Drago Ignjatovic, Daniel W. Bailey, Ljubisa Bajic:
The Wormhole AI Training Processor. 356-358 - David J. Frank, Sudipto Chakraborty, Kevin Tien, Pat Rosno, Thomas Fox, Mark Yeck, Joseph A. Glick, Raphael Robertazzi, Ray Richetta, John F. Bulzacchelli, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv V. Joshi, Shawn D. Chambers, Scott Lekuch, Ken Inoue, Devin Underwood, Dorothy Wisnieff, Christian W. Baks, Donald Bethune, John Timmerwilke, Blake R. Johnson, Brian P. Gaucher, Daniel J. Friedman:
A Cryo-CMOS Low-Power Semi-Autonomous Qubit State Controller in 14nm FinFET Technology. 360-362 - Kiseo Kang, Donggyu Minn, Seunghun Bae, Jaeho Lee, Seongun Bae, Gichang Jung, Seokhyeong Kang, Moonjoo Lee
A Cryo-CMOS Controller IC With Fully Integrated Frequency Generators for Superconducting Qubits. 362-364 - Yatao Peng, Andrea Ruffino, Jad Benserhir, Edoardo Charbon:
A Cryogenic SiGe BiCMOS Hybrid Class B/C Mode-Switching VCO Achieving 201dBc/Hz Figure-of-Merit and 4.2GHz Frequency Tuning Range. 364-366 - Ying Liu, Zhixuan Wang
An 82nW 0.53pJ/SOP Clock-Free Spiking Neural Network with 40µs Latency for AloT Wake-Up Functions Using Ultimate-Event-Driven Bionic Architecture and Computing-in-Memory Technique. 372-374 - Chanwoong Hwang, Hangi Park, Taeho Seong, Jaehyouk Choi:
A 188fsrms-Jitter and -243d8-FoMjitter 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector. 378-380 - Zhong Gao, Jingchu He, Martin Fritz, Jiang Gong, Yiyu Shen, Zhirui Zong, Peng Chen, Gerd Spalink, Ben Eitel, Ken Yamamoto, Robert Bogdan Staszewski, Morteza S. Alavi
A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs. 380-382 - Dihang Yang, David Murphy, Hooman Darabi, Arya Behzad, Asad A. Abidi, Stephen Au, Sraavan R. Mundlapudi, Kejian Shi
A Sub-100MHz Reference-Driven 25-to-28GHz Fractional-N PLL with -250dB FoM. 384-386 - Xinlin Geng, Yibo Tian, Yao Xiao, Zonglin Ye
A 25.8GHz Integer-N PLL With Time-Amplifying Phase-Frequency Detector Achieving 60fsrms Jitter, -252.8dB FoMJ, and Robust Lock Acquisition Performance. 388-390 - Chien-Wei Tseng, Demba Komma, Kuan-Yu Chen, Rohit Rothe, Zhen Feng, Makoto Yasuda, Masaru Kawaminami, Hun-Seok Kim, David T. Blaauw:
A Long-Range Narrowband RF Localization System with a Crystal-Less Frequency-Hopping Receiver. 392-394 - Minyoung Song
A 1.66Gb/s and 5.8pJ/b Transcutaneous IR-UWB Telemetry System with Hybrid Impulse Modulation for Intracortical Brain-Computer Interfaces. 394-396 - Run Chen, Yuzhong Xiao, Yonggang Chen, Hua Xu, Peng Yu, Qi Peng, Xian Li, Xiaofeng Guo, Jianlong Huang, Nansong Li, Xueqing Hu, Rongde Ou, Wenzhe Liu, Bei Chen, Wen Zhang, Xiaofeng Xin, Bingcai Zhao, Zhenqi Chen:
A 6.5-to-10GHz IEEE 802.15.4/4z-Compliant 1T3R UWB Transceiver. 396-398 - Kenichi Shibata, Hiroaki Matsui, Hironori Asano, Yuichi Kusaka, Keisuke Ueda, Noriaki Matsuno, Hisayasu Sato:
A 22nm 0.84mm2 BLE Transceiver With Self IQ-Phase Correction Achieving 39dB Image Rejection and on-Chip Antenna Impedance Tuning. 398-400 - Haijun Shao, Pui-In Mak
A 266µW Bluetooth Low-Energy (BLE) Receiver Featuring an N-Path Passive Balun-LNA and a Pipeline Down-Mixing BB-Extraction Scheme Achieving 77dB SFDR and -3dBm OOB-B-1dB. 400-402 - Milad Moosavifar
A 110µW 2.5kb/s -103dBm-Sensitivity Dual-Chirp Modulated ULP Receiver Achieving -41dB SIR. 402-404 - Keun-Mok Kim, Kyung-Sik Choi, Hyunki Jung, Byeonghun Yun, Subin Kim, Wonkab Oh, Eui-Soo Lee, Sujin Park, Eui-Rim Jeong, Jinho Ko, Sang-Gug Lee:
An LPWAN Radio with a Reconfigurable Data/Duty-Cycled-Wake-Up Receiver. 404-406 - Corentin Pochet, Drew A. Hall
A 4.4μW 2.5kHz-BW 92.1dB-SNDR 3rd-Order VCO-Based ADC With Pseudo Virtual Ground Feedforward Linearization. 408-410 - Yaopeng Hu, Yibo Zhao, Wanyuan Qu, Le Ye, Menglian Zhao, Zhichao Tan:
A 2.87μW 1kHz-BW 94.0dB-SNDR 2-0 MASH ADC Using FIA with Dynamic-Body-Biasing Assisted CLS Technique. 410-412 - Calvin Yoji Lee, Un-Ku Moon:
A 0.0375mm2 203.5µW 108.8dB DR DT Single-Loop DSM Audio ADC Using a Single-Ended Ring-Amplifier-Based Integrator in 180nm CMOS. 412-414 - Qilong Liu
A 5GS/s 360MHz-BW 68dB-DR Continuous-Time 1-1-1 Filtering MASH ΔΣ ADC in 40nm CMOS. 414-416 - Muhammed Bolatkale, Robert Rutten, Hans Brekelmans, Shagun Bajoria, Yihan Gao, Bernard Burdiek, Lucien J. Breems:
A 28nm 6GHz 2b Continuous-Time ΔΣ ADC with -101 dBc THD and 120MHz Bandwidth Using Digital DAC Error Correction. 416-418 - Tzuhan Wang, Tian Xie, Zhe Liu
An 84dB-SNDR Low-OSR 4th-Order Noise-Shaping SAR with an FIA-Assisted EF-CRFF Structure and Noise-Mitigated Push-Pull Buffer-in-Loop Technique. 418-420 - Joseph C. Bardin
Beyond-Classical Computing Using Superconducting Quantum Processors. 422-424 - Chiao Liu, Song Chen, Tsung-Hsun Tsai, Barbara De Salvo, Jorge Gomez:
Augmented Reality - The Next Frontier of Image Sensors and Compute Systems. 426-428 - John J. Wuu, Rahul Agarwal, Michael Ciraula, Carl Dietz, Brett Johnson, Dave Johnson, Russell Schreiber, Raja Swaminathan, Will Walker, Samuel Naffziger:
3D V-Cache: the Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPU. 428-429 - Jian Pang, Yi Zhang
A Power-Efficient 24-to-71 GHz CMOS Phased-Array Receiver Utilizing Harmonic-Selection Technique Supporting 36dB Inter-Band Blocker Rejection for 5G NR. 434-436 - Bodhisatwa Sadhu, Arun Paidimarri
A 24-to-30GHz 256-Element Dual-Polarized 5G Phased Array with Fast Beam-Switching Support for >30, 000 Beams. 436-438 - Kaituo Yang, Chirn Chye Boon, Zhe Liu, Jiaming Piao, Ting Guo, Yangtao Dong, Chenyang Li, Ao Zhou, Zhijie Yang, Xiaoying Wang, Yufeng Liu:
A Hybrid Coupler-First 5GHz Noise-Cancelling Dual-Mode Receiver with +10dBm in-Band IIP3 in Current-Mode and 1.7dB NF in Voltage-Mode. 438-440 - Barosaim Sung, Hyun-Gi Seok
A Single-Path Digital-IF Receiver Supporting Inter/Intra 5-CA with a Single Integer LO-PLL in 14nm CMOS FinFET. 440-442 - Myeong-Jae Park, Ho Sung Cho, Tae-Sik Yun, Sangjin Byeon, Young Jun Koo, Sang-Sic Yoon, Dong-Uk Lee, Seokwoo Choi, Ji Hwan Park, Jinhyung Lee, Kyungjun Cho, Junil Moon, Byung Kuk Yoon, Young Jun Park, Sangmuk Oh, Chang Kwon Lee, Tae-Kyun Kim, Seong-Hee Lee, Hyun-Woo Kim, Yucheon Ju, Seung-Kyun Lim, Seung Geun Baek, Kyo Yun Lee, Sang Hun Lee, Woo Sung We, Seungchan Kim, Yongseok Choi, Seong-Hak Lee, Seung Min Yang, Gunho Lee, In-Keun Kim, Younghyun Jeon, Jae-Hyung Park, Jong Chan Yun, Chanhee Park, Sun-Yeol Kim, Sungjin Kim, Dong-Yeol Lee, Su-Hyun Oh, Taejin Hwang, Junghyun Shin, Yunho Lee, Hyunsik Kim, Jaeseung Lee, Youngdo Hur, Sangkwon Lee, Jieun Jang, Junhyun Chun, Joohwan Cho:
A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization. 444-446 - Daewoong Lee, Hye-Jung Kwon, Daehyun Kwon, Jaehyeok Baek, Chulhee Cho
A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus. 446-448 - Dae-Hyun Kim
A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process. 448-450 - Changjae Moon, Jaeyoung Seo, Myungguk Lee, Iksu Jang
A 20 Gb/s/pin 1.18pJ/b 1149µm2Single-Ended Inverter-based 4-tap Addition-Only Feed-Forward Equalization Transmitter with Improved Robustness to Coefficient Errors in 28nm CMOS. 450-452 - Sangyoon Lee, Jaekwang Yun, Suhwan Kim:
A 78.8fJ/b/mm 12.0Gb/s/Wire Capacitively Driven On-Chip Link Over 5.6mm with an FFE-Combined Ground-Forcing Biasing Technique for DRAM Global Bus Line in 65nm CMOS. 454-456 - Fengbin Tu, Zihan Wu, Yiqi Wang, Ling Liang, Liu Liu
A 28nm 15.59µJ/Token Full-Digital Bitline-Transpose CIM-Based Sparse Transformer Accelerator with Pipeline/Parallel Reconfigurable Modes. 466-468 - Jiho Lee, Sang-Han Lee, Gyeong-Gu Kang, Jae-Hyun Kim
A 130V Triboelectric Energy-Harvesting Interface in .18µm BCD with Scalable Multi-Chip-Stacked Bias-Flip and Daisy-Chained Synchronous Signaling Technique. 474-476 - Sung-Woo Lee, Taejin Jeong, Yonghwan Cho, Jeongdu Yoo, Sung-Kyu Cho, Minkyu Kwon, Dae-Woong Cho, Sang Hee Kang, Jung-Wook Heo, Hyoung-Seok Oh, Sung-Ung Kwak:
A Reconfigurable Series-Parallel Charger for Dual-Battery Applications with 89W 97.7% Efficiency in Direct Charging Mode. 476-478 - Xiaosen Liu, Harish Krishnamurthy, Renzhi Liu, Krishnan Ravichandran, Zakir Ahmed, Nachiket V. Desai, Nicolas Butzen, James W. Tschanz, Vivek De:
A 0.76V Vin Triode Region 4A Analog LDO with Distributed Gain Enhancement and Dynamic Load-Current Tracking in Intel 4 CMOS Featuring Active Feedforward Ripple Shaping and On-Chip Power Noise Analyzer. 478-480 - Shon-Hang Wen, Chuan-Hung Hsiao
A -117dBc THD (-132dBc HD3) and 126dB DR Audio Decoder with Code-Change-Insensitive RT-DEM Algorithm and Circuit Technique for Relaxing Velocity Saturation Effect of Poly Resistors. 482-484 - Wei-Hao Sun, Shih-Hsiung Chien, Tai-Haur Kuo:
A 121dB DR, 0.0017% THD+N, 8× Jitter-Effect Reduction Digital-Input Class-D Audio Amplifier with Supply-Voltage-Scaling Volume Control and Series-Connected DSM. 486-488 - Liuhao Wu, Jiaqi Guo
BatDrone: A 9.83M-focal-points/s 7.76µs-Latency Ultrasound Imaging System with On-Chip Per-Voxel RX Beamfocusing for 7m-Range Drone Applications. 492-494 - Yannick Hopf
A Pitch-Matched ASIC with Integrated 65V TX and Shared Hybrid Beamforming ADC for Catheter-Based High-Frame-Rate 3D Ultrasound Probes. 494-496 - Peng Guo
A 1.2mW/channel 100µm-Pitch-Matched Transceiver ASIC with Boxcar-Integration-Based RX Micro-Beamformer for High-Resolution 3D Ultrasound Imaging. 496-498 - Ajay Singhvi, Aidan Fitzpatrick, Amin Arbabian:
An Electronically Tunable Multi-Frequency Air-Coupled CMUT Receiver Array with sub-100µPa Minimum Detectable Pressure Achieving a 28kb/s Wireless Uplink Across a Water-Air Interface. 498-500 - Taewook Kang, Seungjong Lee, Seungheun Song
A Multimode 157μW 4-Channel 80dBA-SNDR Speech-Recognition Frontend With Self-DOA Correction Adaptive Beamformer. 500-502 - Ji-Soo Chang, Eunsang Jang, Youngkil Choi, Moonkyu Song, Sanghyo Lee, Gi-Jin Kang, Junho Kim, Shin-Wuk Kang, Uijong Song, Chang-Yeon Cho, Junseo Lee, Kyungduck Seo, Seongwook Song, Sung-Ung Kwak:
A 1.05A/m Minimum Magnetic Field Strength Single-Chip Fully Integrated Biometric Smart Card SoC Achieving 1014.7ms Transaction Time with Anti-Spoofing Fingerprint Authentication. 504-506 - Dongseok Im, Gwangtae Park, Zhiyong Li
DSPU: A 281.6mW Real-Time Depth Signal Processing Unit for Deep Learning-Based Dense RGB-D Data Acquisition with Depth Fusion and 3D Bounding Box Extraction in Mobile Platforms. 510-512 - Yihong Zhu, Wenping Zhu, Min Zhu, Chongyang Li, Chenchen Deng, Chen Chen
A 28nm 48KOPS 3.4µJ/Op Agile Crypto-Processor for Post-Quantum Cryptography on Multi-Mathematical Problems. 514-516 - Saurav Maji, Utsav Banerjee, Samuel H. Fuller, Anantha P. Chandrakasan:
A ThreshoId-ImpIementation-Based Neural-Network Accelerator Securing Model Parameters and Inputs Against Power Side-Channel Attacks. 518-520
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