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Mircea R. Stan
Mircea Stan
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- affiliation: University of Virginia, Charlottesville, USA
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2020 – today
- 2024
- [c152]Faiyaz E. Mullick, Rahul Sreekumar, Md Golam Morshed, Samiran Ganguly, Mircea Stan, Avik W. Ghosh:
Double magnetic tunnel junction based ∑Δ∑ hardware neuron. DRC 2024: 1-2 - [c151]Jun Yin, Elisa Pantoja, Yimin Gao, Mircea R. Stan:
A Feedback Self-adaptive Body Biasing-based RF-DC Rectifier for Highly-sensitive RF Energy Harvesting. ISCAS 2024: 1-5 - [c150]Rahul Sreekumar, Minseong Park, Mohammad Nazmus Sakib, Bhupendra S. Reniwal, Kyusang Lee, Mircea R. Stan:
EASI-CiM: Event-driven Asynchronous Stream-based Image classifier with Compute-in-Memory kernels. ISQED 2024: 1-8 - [c149]Muhammed Ceylan Morgül, Xinfei Guo, Mircea Stan:
Unveiling Proactive Recovery's Preventative Impact on NAND Flash Wearout. ISVLSI 2024: 712-716 - [c148]Rahul Sreekumar, Faiyaz E. Mullick, Md Golam Morshed, Avik W. Ghosh, Mircea R. Stan:
Exploring Noise- Resilient Spiking Neural Encoding using ∑†∑ Neurons. MWSCAS 2024: 131-135 - [i7]Runxi Wang, Jun-Han Han, Mircea Stan, Xinfei Guo:
Hot-LEGO: Architect Microfluidic Cooling Equipped 3DICs with Pre-RTL Thermal Simulation. CoRR abs/2403.20050 (2024) - 2023
- [j56]Mircea R. Stan
:
Editorial New Beginnings for IEEE TVLSI. IEEE Trans. Very Large Scale Integr. Syst. 31(8): 1087-1113 (2023) - [j55]Mircea R. Stan:
Editorial Rolling Out the IEEE TVLSI EDICS. IEEE Trans. Very Large Scale Integr. Syst. 31(12): 1879-1881 (2023) - [j54]Sankatali Venkateswarlu
Impact of 3-D Integration on Thermal Performance of RISC-V MemPool Multicore SOC. IEEE Trans. Very Large Scale Integr. Syst. 31(12): 1896-1904 (2023) - [c147]Lingxi Wu, Rahul Sreekumar, Rasool Sharifi, Kevin Skadron
Hardware Trojans in eNVM Neuromorphic Devices. DATE 2023: 1-6 - [c146]Sergiu Mosanu
FreezeTime: Towards System Emulation through Architectural Virtualization. FPGA 2023: 234 - [c145]Xiaotian Zhao
Design Space Exploration of Layer-Wise Mixed-Precision Quantization with Tightly Integrated Edge Inference Units. ACM Great Lakes Symposium on VLSI 2023: 467-471 - [c144]Runxi Wang
Hot-LEGO: Architect Microfluidic Cooling Equipped 3DIC with Pre-RTL Thermal Simulation. IGSC 2023: 14-17 - [c143]Sergiu Mosanu, Joshua Fixelle, Mohammad Nazmus Sakib, Kevin Skadron
FreezeTime: Towards System Emulation through Architectural Virtualization. IPDPS Workshops 2023: 129-136 - [c142]Jun Yin
A Low Power SRAM with Fully Dynamic Leakage Suppression for IoT Nodes. ISQED 2023: 1-8 - [c141]Yi Zheng, Joshua Fixelle, Pingyi Huo, Mircea Stan
ISVABI: In-Storage Video Analytics Engine with Block Interface. LCTES 2023: 111-121 - [c140]Elisa Pantoja, Rahul Sreekumar, Sergiu Mosanu
Virtualized Controller for Computational RFID-based IoT Sensors. RFID 2023: 54-59 - [c139]Yimin Gao, Sergiu Mosanu, Mohammad Nazmus Sakib, Vaibhav Verma
LiteAIR5: A System-Level Framework for the Design and Modeling of AI-extended RISC-V Cores. SOCC 2023: 1-6 - [c138]Elisa Pantoja, Mircea Stan:
Advancing Wireless IoT Sensor Networks With Edge-Powered RFID Devices. UEMCON 2023: 632-636 - 2022
- [j53]Xinfei Guo
Agile-AES: Implementation of configurable AES primitive with agile design approach. Integr. 85: 87-96 (2022) - [j52]Vaibhav Verma
EXTREM-EDGE - EXtensions To RISC-V for Energy-efficient ML inference at the EDGE of IoT. Sustain. Comput. Informatics Syst. 35: 100742 (2022) - [j51]Sankatali Venkateswarlu
Thermal Performance Analysis of Mempool RISC-V Multicore SoC. IEEE Trans. Very Large Scale Integr. Syst. 30(11): 1668-1676 (2022) - [c137]Sergiu Mosanu
PiMulator: a Fast and Flexible Processing-in-Memory Emulation Platform. DATE 2022: 1473-1478 - [c136]Marzieh Lenjani, Alif Ahmed, Mircea Stan
Gearbox: a case for supporting accumulation dispatching and hybrid partitioning in PIM-based accelerators. ISCA 2022: 218-230 - [c135]Mohammad Nazmus Sakib, Rahul Sreekumar, Xinyuan Zhu, Tommy Tracy II, Mircea R. Stan
Processing-in-Memory with Temporal Encoding. ISVLSI 2022: 56-61 - [c134]Muhammed Ceylan Morgül, Xinfei Guo, Mircea Stan
Towards Everlasting Flash: Preventing Permanent Flash Cell Damage using Circadian Rhythms. ISVLSI 2022: 376-379 - [c133]Yi Zheng, Joshua Fixelle, Nagadastagiri Challapalle, Pingyi Huo, Zhaoyan Shen, Zili Shao, Mircea Stan, Vijaykrishnan Narayanan:
ISKEVA: in-SSD key-value database engine for video analytics applications. LCTES 2022: 50-60 - [c132]Muhammed Ceylan Morgül, Mircea R. Stan
Scheduling Active and Accelerated Recovery to Combat Aging in Integrated Circuits. MWSCAS 2022: 1-5 - 2021
- [c131]Rahul Sreekumar, Mircea R. Stan
Microarchitecture Optimization for Asynchronous Stochastic Computing. ICECS 2021: 1-6 - [c130]Jun-Han Han, Robert E. West, Karina Torres-Castro
Power and Thermal Modeling of In-3D-Memory Computing. ISDCS 2021: 1-4 - [c129]Mohammad Nazmus Sakib, Rahul Sreekumar, Vaibhav Verma
ATCPiM: Analog to Time Coded Processing in Memory for IoT at the Edge. WF-IoT 2021: 704-709 - 2020
- [j50]Nikolaos S. Voros, Mircea Stan, Michael Hübner, Georgios Keramidas:
VLSI for Next Generation CE. IEEE Consumer Electron. Mag. 9(3): 88-89 (2020) - [j49]Patricia Gonzalez-Guerrero
Towards on-node Machine Learning for Ultra-low-power Sensors Using Asynchronous Σ Δ Streams. ACM J. Emerg. Technol. Comput. Syst. 16(4): 44:1-44:20 (2020) - [j48]Somayeh Rahimipour
Low-Power, Highly Reliable Dynamic Thermal Management by Exploiting Approximate Computing. IEEE Trans. Very Large Scale Integr. Syst. 28(10): 2210-2222 (2020) - [c128]Elaheh Sadredini
FlexAmata: A Universal and Efficient Adaption of Applications to Spatial Automata Processing Accelerators. ASPLOS 2020: 219-234 - [c127]Mustafa Altun, Ismail Cevik, Ahmet Erten
Nano-Crossbar based Computing: Lessons Learned and Future Directions. DATE 2020: 382-387 - [c126]Reza Rahimi, Elaheh Sadredini
Grapefruit: An Open-Source, Full-Stack, and Customizable Automata Processing on FPGAs. FCCM 2020: 138-147 - [c125]Elaheh Sadredini
Impala: Algorithm/Architecture Co-Design for In-Memory Multi-Stride Pattern Matching. HPCA 2020: 86-98 - [c124]Marzieh Lenjani, Patricia Gonzalez-Guerrero, Elaheh Sadredini
Fulcrum: A Simplified Control and Access Mechanism Toward Flexible and Practical In-Situ Accelerators. HPCA 2020: 556-569 - [c123]Rafailia-Eleni Karamani, Iosif-Angelos Fyrigos, Vasileios G. Ntinas
Memristive Learning Cellular Automata: Theory and Applications. MOCAST 2020: 1-5 - [i6]Rafailia-Eleni Karamani, Iosif-Angelos Fyrigos, Vasileios G. Ntinas, Orestis Liolis, Giorgos Dimitrakopoulos, Mustafa Altun, Andrew Adamatzky, Mircea R. Stan, Georgios Ch. Sirakoulis:
Memristive Learning Cellular Automata: Theory and Applications. CoRR abs/2003.06983 (2020) - [i5]Hamed Vakili, Mohammad Nazmus Sakib, Samiran Ganguly, Mircea Stan, Matthew W. Daniels, Advait Madhavan, Mark D. Stiles, Avik W. Ghosh:
Temporal Memory with Magnetic Racetracks. CoRR abs/2005.10704 (2020)
2010 – 2019
- 2019
- [j47]Elaheh Sadredini
A Scalable and Efficient In-Memory Interconnect Architecture for Automata Processing. IEEE Comput. Archit. Lett. 18(2): 87-90 (2019) - [j46]Chunkun Bo, Vinh Dang, Ted Xie, Jack Wadden, Mircea Stan
Automata Processing in Reconfigurable Architectures: In-the-Cloud Deployment, Cross-Platform Evaluation, and Fast Symbol-Only Reconfiguration. ACM Trans. Reconfigurable Technol. Syst. 12(2): 9:1-9:25 (2019) - [j45]Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 253-280 (2019) - [j44]Somayeh Rahimipour
MTTF Enhancement Power-C4 Bump Placement Optimization. IEEE Trans. Very Large Scale Integr. Syst. 27(7): 1633-1639 (2019) - [c122]Patricia Gonzalez-Guerrero, Mircea R. Stan
Asynchronous Stochastic Computing. ACSSC 2019: 280-285 - [c121]Stephen G. Wilson, Patricia Gonzalez-Guerrero, Mircea Stan
Fourier-based Error Analysis for Computing with Asynchronous Sigma-Delta Streams. ACSSC 2019: 373-377 - [c120]Eric Cheng, Daniel Mueller-Gritschneder
Cross-Layer Resilience: Challenges, Insights, and the Road Ahead. DAC 2019: 198 - [c119]Sergiu Mosanu
Flexi-AES: A Highly-Parameterizable Cipher for a Wide Range of Design Constraints. FCCM 2019: 338 - [c118]Patricia Gonzalez-Guerrero, Tommy Tracy II, Xinfei Guo, Mircea R. Stan
Towards low-power random forest using asynchronous computing with streams. IGSC 2019: 1-5 - [c117]Marzieh Lenjani, Patricia Gonzalez-Guerrero, Elaheh Sadredini
An Overflow-free Quantized Memory Hierarchy in General-purpose Processors. IISWC 2019: 203-215 - [c116]Patricia Gonzalez-Guerrero, Xinfei Guo, Mircea R. Stan
ASC-FFT: Area-Efficient Low-Latency FFT Design Based on Asynchronous Stochastic Computing. LASCAS 2019: 117-120 - [c115]Elaheh Sadredini
eAP: A Scalable and Efficient In-Memory Accelerator for Automata Processing. MICRO 2019: 87-99 - [c114]Patricia Gonzalez-Guerrero, Mircea R. Stan
Asynchronous Stream Computing for Low Power IoT. MWSCAS 2019: 1135-1138 - [c113]Patricia Gonzalez-Guerrero, Stephen G. Wilson, Mircea R. Stan
Error-latency Trade-off for Asynchronous Stochastic Computing with ΣΔ Streams for the IoT. SoCC 2019: 97-102 - 2018
- [j43]Kevin Angstadt
MNCaRT: An Open-Source, Multi-Architecture Automata-Processing Research and Execution Ecosystem. IEEE Comput. Archit. Lett. 17(1): 84-87 (2018) - [j42]Eric Cheng
Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(9): 1839-1852 (2018) - [j41]Alec Roelke
Controlling the Reliability of SRAM PUFs With Directed NBTI Aging and Recovery. IEEE Trans. Very Large Scale Integr. Syst. 26(10): 2016-2026 (2018) - [c112]Mateja Putic, Swagath Venkataramani, Schuyler Eldridge
Dyhard-DNN: even more DNN acceleration with dynamic hardware reconfiguration. DAC 2018: 14:1-14:6 - [c111]Yunfei Gu, Dengxue Yan, Vaibhav Verma
SRAM based opportunistic energy efficiency improvement in dual-supply near-threshold processors. DAC 2018: 41:1-41:6 - [c110]Alec Roelke, Xinfei Guo, Mircea Stan
OldSpot: A Pre-RTL Model for Fine-Grained Aging and Lifetime Optimization. ICCD 2018: 148-151 - [c109]Patricia Gonzalez-Guerrero, Xinfei Guo, Mircea Stan
SC-SD: Towards Low Power Stochastic Computing Using Sigma Delta Streams. ICRC 2018: 1-8 - [c108]Samiran Ganguly, Yunfei Gu, Yunkun Xie
Reservoir Computing Based Neural Image Filters. IECON 2018: 3206-3210 - [c107]Jack Wadden, Tommy Tracy II, Elaheh Sadredini
AutomataZoo: A Modern Automata Processing Benchmark Suite. IISWC 2018: 13-24 - [c106]Xinfei Guo, Vaibhav Verma
When "things" get older: Exploring circuit aging in IoT applications. ISQED 2018: 296-301 - [c105]Divya Akella Kamakshi, Xinfei Guo, Harsh N. Patel, Mircea R. Stan
A post-silicon hold time closure technique using data-path tunable-buffers for variation-tolerance in sub-threshold designs. ISQED 2018: 341-346 - [c104]Muhammed Ceylan Morgül, Onur Tunali
Integrated Synthesis Methodology for Crossbar Arrays. NANOARCH 2018: 91-97 - [c103]Alec Roelke, Mircea R. Stan
Co-Optimizing CPUs and Accelerators in Constrained Systems. SoCC 2018: 254-259 - [i4]Samiran Ganguly, Yunfei Gu, Mircea R. Stan, Avik W. Ghosh:
Hardware based Spatio-Temporal Neural Processing Backend for Imaging Sensors: Towards a Smart Camera. CoRR abs/1803.08635 (2018) - [i3]Samiran Ganguly, Yunfei Gu, Yunkun Xie, Mircea R. Stan, Avik W. Ghosh, Nibir K. Dhar:
Reservoir Computing based Neural Image Filters. CoRR abs/1809.02651 (2018) - 2017
- [j40]Xinfei Guo
Implications of accelerated self-healing as a key design knob for cross-layer resilience. Integr. 56: 167-180 (2017) - [j39]Xinfei Guo
Back to the Future: Digital Circuit Design in the FinFET Era. J. Low Power Electron. 13(3): 338-355 (2017) - [j38]Mateja Putic, A. J. Varshneya, Mircea R. Stan
Hierarchical Temporal Memory on the Automata Processor. IEEE Micro 37(1): 52-59 (2017) - [j37]Mohamed El-Hadedy, Xinfei Guo
Dual-Data Rate Transpose-Memory Architecture Improves the Performance, Power and Area of Signal-Processing Systems. J. Signal Process. Syst. 88(2): 167-184 (2017) - [c102]Mohamed El-Hadedy, Xinfei Guo
PPE-ARX: Area- and power-efficient VLIW programmable processing element for IoT crypto-systems. AHS 2017: 153-160 - [c101]Xinfei Guo
Deep Healing: Ease the BTI and EM Wearout Crisis by Activating Recovery. DSN Workshops 2017: 184-191 - [c100]Ted Xie, Vinh Dang, Jack Wadden, Kevin Skadron
REAPR: Reconfigurable engine for automata processing. FPL 2017: 1-8 - [c99]Eric Cheng, Jacob A. Abraham, Pradip Bose, Alper Buyuktosunoglu, Keith A. Campbell, Deming Chen, Chen-Yong Cher, Hyungmin Cho, Binh Q. Le, Klas Lilja, Shahrzad Mirkhani, Kevin Skadron
Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights. ICCD 2017: 593-596 - [c98]Alec Roelke, Runjie Zhang, Kaushik Mazumdar, Ke Wang, Kevin Skadron
Pre-RTL Voltage and Power Optimization for Low-Cost, Thermally Challenged Multicore Chips. ICCD 2017: 597-600 - [c97]Ramon Bertran
Very Low Voltage (VLV) Design. ICCD 2017: 601-604 - [c96]Mircea Stan:
Panel discussion: Autonomy, technology, safety - Where will automotive electronics go in the next decade? SoCC 2017: 1 - [i2]Eric Cheng, Shahrzad Mirkhani, Lukasz G. Szafaryn, Chen-Yong Cher, Hyungmin Cho, Kevin Skadron, Mircea R. Stan, Klas Lilja, Jacob A. Abraham, Pradip Bose, Subhasish Mitra:
Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience). CoRR abs/1709.09921 (2017) - 2016
- [j36]Babak Falsafi, Mircea Stan
Near-Memory Data Services. IEEE Micro 36(1): 6-13 (2016) - [j35]Runjie Zhang, Brett H. Meyer, Ke Wang, Mircea R. Stan
Tolerating the Consequences of Multiple EM-Induced C4 Bump Failures. IEEE Trans. Very Large Scale Integr. Syst. 24(6): 2335-2344 (2016) - [c95]Xinfei Guo
Work hard, sleep well - Avoid irreversible IC wearout with proactive rejuvenation. ASP-DAC 2016: 649-654 - [c94]Ke Wang, Kevin Angstadt, Chunkun Bo, Nathan Brunelle, Elaheh Sadredini
An overview of micron's automata processor. CODES+ISSS 2016: 14:1-14:3 - [c93]Eric Cheng, Shahrzad Mirkhani, Lukasz G. Szafaryn, Chen-Yong Cher, Hyungmin Cho, Kevin Skadron
Clear: cross-layer exploration for architecting resilience combining hardware and software techniques to tolerate soft errors in processor cores. DAC 2016: 68:1-68:6 - [c92]Jack Wadden, Nathan Brunelle, Ke Wang, Mohamed El-Hadedy, Gabriel Robins, Mircea Stan
Generating efficient and high-quality pseudo-random behavior on Automata Processors. ICCD 2016: 622-629 - [c91]Jack Wadden, Vinh Dang, Nathan Brunelle, Tommy Tracy II, Deyuan Guo, Elaheh Sadredini
ANMLzoo: a benchmark suite for exploring bottlenecks in automata processing engines and architectures. IISWC 2016: 105-166 - [c90]Alec Roelke, Mircea R. Stan
Attacking an SRAM-Based PUF through Wearout. ISVLSI 2016: 206-211 - [c89]Andrew Whetzel, Mircea R. Stan
Gate Overdrive with Split-Circuit Biasing to Substitute for Body Biasing in FinFET and UTB FDSOI Circuits. ISVLSI 2016: 467-472 - [i1]Eric Cheng, Shahrzad Mirkhani, Lukasz G. Szafaryn, Chen-Yong Cher, Hyungmin Cho, Kevin Skadron, Mircea R. Stan, Klas Lilja, Jacob A. Abraham, Pradip Bose, Subhasish Mitra:
CLEAR: Cross-Layer Exploration for Architecting Resilience - Combining Hardware and Software Techniques to Tolerate Soft Errors in Processor Cores. CoRR abs/1604.03062 (2016) - 2015
- [c88]Runjie Zhang, Kaushik Mazumdar, Brett H. Meyer, Ke Wang, Kevin Skadron
A cross-layer design exploration of charge-recycled power-delivery in many-layer 3d-IC. DAC 2015: 133:1-133:6 - [c87]Ke Wang, Yanjun Qi, Jeffrey J. Fox
Association Rule Mining with the Micron Automata Processor. IPDPS 2015: 689-699 - [c86]Runjie Zhang, Kaushik Mazumdar, Brett H. Meyer, Ke Wang, Kevin Skadron
Transient voltage noise in charge-recycled power delivery networks for many-layer 3D-IC. ISLPED 2015: 152-158 - [c85]Kaushik Mazumdar, Steven Bartling, Sudhanshu Khanna, Mircea R. Stan
A digitally-controlled power-aware low-dropout regulator to reduce standby current drain in ultra-low-power MCU. ISQED 2015: 98-102 - [c84]Elena K. Weinberg, Mircea R. Stan
SymmTop: A Symmetric Circuit Topology for Ultra Low Power Wide Temperature-Range Applications. ISVLSI 2015: 585-590 - 2014
- [c83]Ke Wang, Brett H. Meyer, Runjie Zhang, Kevin Skadron
Walking pads: Fast power-supply pad-placement optimization. ASP-DAC 2014: 537-543 - [c82]Mehdi Kabir, Mircea R. Stan
Computing with Hybrid CMOS/STO Circuits. DAC 2014: 73:1-73:6 - [c81]Ke Wang, Brett H. Meyer, Runjie Zhang, Mircea R. Stan
Walking Pads: Managing C4 Placement for Transient Voltage Noise Minimization. DAC 2014: 126:1-126:6 - [c80]Xinfei Guo
Modeling and Experimental Demonstration of Accelerated Self-Healing Techniques. DAC 2014: 171:1-171:6 - [c79]Runjie Zhang, Ke Wang, Brett H. Meyer, Mircea R. Stan
Architecture implications of pads as a scarce resource. ISCA 2014: 373-384 - [c78]Yingbo Zhao, Yintang Yang, Kaushik Mazumdar, Xinfei Guo
A multi-output on-chip switched-capacitor DC-DC converter for near- and sub-threshold power modes. ISCAS 2014: 1632-1635 - [c77]Mircea R. Stan
Spin torque nano oscillators as key building blocks for the Systems-on-Chip of the future. NANOARCH 2014: 37-38 - 2013
- [j34]Karthik Sankaranarayanan, Brett H. Meyer, Wei Huang, Robert J. Ribando, Hossein Haj-Hariri, Mircea R. Stan
Architectural implications of spatial thermal filtering. Integr. 46(1): 44-56 (2013) - [j33]Vidyabhushan Mohan, Trevor Bunker, Laura M. Grupp, Sudhanva Gurumurthi, Mircea R. Stan
Modeling Power Consumption of NAND Flash Memories Using FlashPower. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(7): 1031-1044 (2013) - [c76]Mircea Stan:
Breaking power delivery walls using voltage stacking. ISVLSI 2013: 212 - [c75]Mircea R. Stan
Nano-pattemed coupled spin torque nano oscillator (STNO) arrays - A potentially disruptive multipurpose nanotechnology. NEWCAS 2013: 1-4 - 2012
- [j32]Stuart N. Wooters, Adam C. Cabe, Zhenyu Qi, Jiajing Wang, Randy W. Mann, Benton H. Calhoun, Mircea R. Stan
Tracking On-Chip Age Using Distributed, Embedded Sensors. IEEE Trans. Very Large Scale Integr. Syst. 20(11): 1974-1985 (2012) - [c74]Kaushik Mazumdar, Mircea R. Stan
Breaking the 3D IC power delivery wall. ACSCC 2012: 741-746 - [c73]Kaushik Mazumdar, Mircea R. Stan
Breaking the power delivery wall using voltage stacking. ACM Great Lakes Symposium on VLSI 2012: 51-54 - [c72]Stevo D. Bailey, Mircea R. Stan
A new taxonomy for reconfigurable prefix adders. ISCAS 2012: 1227-1230 - [c71]Mircea R. Stan
Self-assembled multiferroic magnetic QCA structures for low power systems. ISCAS 2012: 2525-2528 - [c70]Mehdi Sadi, Mircea Stan
Design of near threshold All Digital Delay Locked Loops. SoCC 2012: 137-142 - [c69]Gregory G. Faust, Runjie Zhang, Kevin Skadron
ArchFP: Rapid prototyping of pre-RTL floorplans. VLSI-SoC 2012: 183-188 - 2011
- [j31]Wei Huang, Malcolm Allen-Ware, John B. Carter, Mircea R. Stan
Temperature-Aware Architecture: Lessons and Opportunities. IEEE Micro 31(3): 82-86 (2011) - [j30]Wei Huang, Karthick Rajamani, Mircea R. Stan
Scaling with Design Constraints: Predicting the Future of Big Chips. IEEE Micro 31(4): 16-29 (2011) - [j29]Karthik Sankaranarayanan, Brett H. Meyer, Mircea R. Stan
Thermal benefit of multi-core floorplanning: A limits study. Sustain. Comput. Informatics Syst. 1(4): 286-293 (2011) - [c68]Mehdi Kabir, Mircea R. Stan
RAMA: a self-assembled multiferroic magnetic QCA for low power systems. ACM Great Lakes Symposium on VLSI 2011: 25-30 - [c67]Adam C. Cabe, Mircea R. Stan
Experimental demonstration of standby power reduction using voltage stacking in an 8Kb embedded FDSOI SRAM. ACM Great Lakes Symposium on VLSI 2011: 399-402 - [c66]Clinton Wills Smullen IV, Vidyabhushan Mohan, Anurag Nigam, Sudhanva Gurumurthi, Mircea R. Stan
Relaxing non-volatility for fast and energy-efficient STT-RAM caches. HPCA 2011: 50-61 - [c65]Clinton Wills Smullen IV, Anurag Nigam, Sudhanva Gurumurthi, Mircea R. Stan
The STeTSiMS STT-RAM simulation and modeling system. ICCAD 2011: 318-325 - [c64]Anurag Nigam, Clinton Wills Smullen IV, Vidyabhushan Mohan, Eugene Chen, Sudhanva Gurumurthi, Mircea R. Stan:
Delivering on the promise of universal memory for spin-transfer torque RAM (STT-RAM). ISLPED 2011: 121-126 - [c63]Taniya Siddiqua, Sudhanva Gurumurthi, Mircea R. Stan
Modeling and analyzing NBTI in the presence of Process Variation. ISQED 2011: 28-35 - 2010
- [j28]Stuart A. Wolf, Jiwei Lu, Mircea R. Stan
The Promise of Nanomagnetics and Spintronics for Future Logic and Universal Memory. Proc. IEEE 98(12): 2155-2168 (2010) - [c62]Jiajing Wang, Satyanand Nalam, Zhenyu Qi, Randy W. Mann, Mircea R. Stan
Improving SRAM Vmin and yield by using variation-aware BTI stress. CICC 2010: 1-4 - [c61]Adam C. Cabe, Zhenyu Qi, Mircea R. Stan
Stacking SRAM banks for ultra low power standby mode operation. DAC 2010: 699-704 - [c60]Zhenyu Qi, Jiajing Wang, Adam C. Cabe, Stuart N. Wooters, Travis N. Blalock, Benton H. Calhoun, Mircea R. Stan
SRAM-based NBTI/PBTI sensor system design. DAC 2010: 849-852 - [c59]Vidyabhushan Mohan, Sudhanva Gurumurthi, Mircea R. Stan
FlashPower: A detailed power model for NAND flash memory. DATE 2010: 502-507 - [c58]Mircea Stan:
Reliability/wearout-aware design. Green Computing Conference 2010: 523 - [c57]Vidyabhushan Mohan, Taniya Siddiqua, Sudhanva Gurumurthi, Mircea R. Stan:
How I Learned to Stop Worrying and Love Flash Endurance. HotStorage 2010 - [c56]Zhenyu Qi, Brett H. Meyer, Wei Huang, Robert J. Ribando, Kevin Skadron
Temperature-to-power mapping. ICCD 2010: 384-389
2000 – 2009
- 2009
- [j27]Sudhanva Gurumurthi, Sriram Sankar, Mircea R. Stan
Using Intradisk Parallelism to Build Energy-Efficient Storage Systems. IEEE Micro 29(1): 50-61 (2009) - [j26]Sriram Sankar, Yan Zhang, Sudhanva Gurumurthi, Mircea R. Stan
Sensitivity-Based Optimization of Disk Architecture. IEEE Trans. Computers 58(1): 69-81 (2009) - [c55]Mircea R. Stan
Electromigration-aware design. ECCTD 2009: 786-789 - [c54]Mircea R. Stan
Graphene Devices, Interconnect and Circuits - Challenges and Opportunities. ISCAS 2009: 69-72 - [c53]Wei Huang, Kevin Skadron
Differentiating the roles of IR measurement and simulation for power and temperature-aware design. ISPASS 2009: 1-10 - [c52]Adam C. Cabe, Zhenyu Qi, Stuart N. Wooters, Travis N. Blalock, Mircea R. Stan
Small embeddable NBTI sensors (SENS) for tracking on-chip performance decay. ISQED 2009: 1-6 - 2008
- [j25]Wei Huang, Karthik Sankaranarayanan, Kevin Skadron
Accurate, Pre-RTL Temperature-Aware Design Using a Parameterized, Geometric Thermal Model. IEEE Trans. Computers 57(9): 1277-1288 (2008) - [c51]Wei Huang, Mircea R. Stan
Many-core design from a thermal perspective. DAC 2008: 746-749 - [c50]Zhenyu Qi, Mircea R. Stan
NBTI resilient circuits using adaptive body biasing. ACM Great Lakes Symposium on VLSI 2008: 285-290 - [c49]Sriram Sankar, Sudhanva Gurumurthi, Mircea R. Stan
Intra-disk Parallelism: An Idea Whose Time Has Come. ISCA 2008: 303-314 - [c48]Sriram Sankar, Sudhanva Gurumurthi, Mircea R. Stan:
Sensitivity Based Power Management of Enterprise Storage Systems. MASCOTS 2008: 93-102 - 2007
- [j24]Garrett S. Rose
Designing CMOS/molecular memories while considering device parameter variations. ACM J. Emerg. Technol. Comput. Syst. 3(1): 3 (2007) - [j23]Alain E. Kaloyeros, Mircea R. Stan
Conformational Molecular Switches for Post-CMOS Nanoelectronics. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(11): 2345-2352 (2007) - [j22]Garrett S. Rose
A Programmable Majority Logic Array Using Molecular Scale Electronics. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(11): 2380-2390 (2007) - [j21]Zhijian Lu, Wei Huang, Mircea R. Stan
Interconnect Lifetime Prediction for Reliability-Aware Systems. IEEE Trans. Very Large Scale Integr. Syst. 15(2): 159-172 (2007) - [c47]Yan Zhang, Sudhanva Gurumurthi, Mircea R. Stan:
SODA: Sensitivity Based Optimization of Disk Architecture. DAC 2007: 865-870 - [c46]Yan Zhang, Mircea R. Stan
Temperature-aware circuit design using adaptive body biasing. ACM Great Lakes Symposium on VLSI 2007: 84-89 - [c45]Matthew M. Ziegler, Gary S. Ditlow, Stephen V. Kosonocky, Zhenyu Qi, Mircea R. Stan
Structured and tuned array generation (STAG) for high-performance random logic. ACM Great Lakes Symposium on VLSI 2007: 257-262 - [c44]Zhenyu Qi, Matthew M. Ziegler, Stephen V. Kosonocky, Jan M. Rabaey, Mircea R. Stan
Multi-Dimensional Circuit and Micro-Architecture Level Optimization. ISQED 2007: 275-280 - [c43]Zhenyu Qi, Mircea R. Stan
Accurate Back-of-the-Envelope Transistor Model for Deep Sub-micron MOS. MSE 2007: 75-76 - [c42]Mircea R. Stan
Teaching Top-Down ASIC/SoC Design vs Bottom-Up Custom VLSI. MSE 2007: 89-90 - 2006
- [j20]Wei Huang, Shougata Ghosh, Sivakumar Velusamy, Karthik Sankaranarayanan, Kevin Skadron
HotSpot: A Compact Thermal Modeling Methodology for Early-Stage VLSI Design. IEEE Trans. Very Large Scale Integr. Syst. 14(5): 501-513 (2006) - [c41]Zhijian Lu, Yan Zhang, Mircea R. Stan
Procrastinating voltage scheduling with discrete frequency sets. DATE 2006: 456-461 - [c40]Garrett S. Rose
A programmable majority logic array using molecular scale electronics. FPGA 2006: 225 - [c39]Garrett S. Rose
Design approaches for hybrid CMOS/molecular memory based on experimental device data. ACM Great Lakes Symposium on VLSI 2006: 2-7 - [c38]Zhenyu Qi, Wei Huang, Adam C. Cabe, Wenqian Wu, Yan Zhang, Garrett S. Rose, Mircea R. Stan
A Design Methodology for a Low-Power, Temperature-Aware SoC Developed for Medical Image Processors. SoCC 2006: 111-112 - [c37]Mircea R. Stan
Hybrid CMOS/Molecular Electronic Circuits. VLSI Design 2006: 703-708 - [e2]Wolfgang Nebel, Mircea R. Stan, Anand Raghunathan, Jörg Henkel, Diana Marculescu:
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006. ACM 2006, ISBN 1-59593-462-6 [contents] - 2005
- [j19]Karthik Sankaranarayanan, Sivakumar Velusamy, Mircea R. Stan, Kevin Skadron:
A Case for Thermal-Aware Floorplanning at the Microarchitectural Level. J. Instr. Level Parallelism 7 (2005) - [j18]Zhijian Lu, John C. Lach, Mircea R. Stan
Improved Thermal Management with Reliability Banking. IEEE Micro 25(6): 40-49 (2005) - [c36]Yan Zhang, Zhijian Lu, John C. Lach, Kevin Skadron
Optimal procrastinating voltage scheduling for hard real-time systems. DAC 2005: 905-908 - [c35]Sivakumar Velusamy, Wei Huang, John C. Lach, Mircea R. Stan
Monitoring Temperature in FPGA based SoCs. ICCD 2005: 634-640 - [c34]Yan Zhang, Travis N. Blalock, Mircea R. Stan
A three-level toggle-avoid bus signaling scheme. ISCAS (2) 2005: 1843-1846 - [c33]Wei Huang, Eric Humenay, Kevin Skadron
The need for a full-chip and package thermal model for thermally optimized IC designs. ISLPED 2005: 245-250 - 2004
- [j17]Kevin Skadron
Temperature-aware microarchitecture: Modeling and implementation. ACM Trans. Archit. Code Optim. 1(1): 94-125 (2004) - [j16]Dharmesh Parikh, Kevin Skadron
Power-Aware Branch Prediction: Characterization and Design. IEEE Trans. Computers 53(2): 168-186 (2004) - [j15]Garrett S. Rose
Large-signal two-terminal device model for nanoelectronic circuit analysis. IEEE Trans. Very Large Scale Integr. Syst. 12(11): 1201-1208 (2004) - [c32]Lei He, Weiping Liao, Mircea R. Stan
System level leakage reduction considering the interdependence of temperature and leakage. DAC 2004: 12-17 - [c31]Wei Huang, Mircea R. Stan
Compact thermal modeling for temperature-aware design. DAC 2004: 878-883 - [c30]Yingmin Li, Dharmesh Parikh, Yan Zhang, Karthik Sankaranarayanan, Mircea R. Stan
State-Preserving vs. Non-State-Preserving Leakage Control in Caches. DATE 2004: 22-29 - [c29]Matthew M. Ziegler, Mircea R. Stan
A Unified Design Space for Regular Parallel Prefix Adders. DATE 2004: 1386-1387 - [c28]Zhijian Lu, Wei Huang, John C. Lach, Mircea R. Stan
Interconnect lifetime prediction under dynamic stress for reliability-aware design. ICCAD 2004: 327-334 - [c27]Mircea R. Stan:
Systolic counters with unique zero state. ISCAS (2) 2004: 909-912 - [c26]Mircea R. Stan
Perfect 3-Limited-Weight Code for Low Power I/O. PATMOS 2004: 79-89 - [c25]Mircea R. Stan
Non-Manhattan maze routing. SBCCI 2004: 260-265 - 2003
- [j14]Mircea R. Stan
Guest Editors' Introduction: Power-Aware Computing. Computer 36(12): 35-38 (2003) - [j13]Zhijian Lu, John C. Lach, Mircea R. Stan
Alloyed Branch History: Combining Global and Local Branch History for Robust Performance. Int. J. Parallel Program. 31(2): 137-177 (2003) - [j12]Kevin Skadron
Temperature-Aware Computer Systems: Opportunities and Challenges. IEEE Micro 23(6): 52-61 (2003) - [j11]Mircea R. Stan
HotSpot: a dynamic compact thermal model at the processor-architecture level. Microelectron. J. 34(12): 1153-1165 (2003) - [j10]Mircea R. Stan
Molecular electronics: from devices and interconnect to circuits and architecture. Proc. IEEE 91(11): 1940-1957 (2003) - [c24]Zhijian Lu, John C. Lach, Mircea R. Stan
Reducing Multimedia Decode Power using Feedback Control. ICCD 2003: 489- - [c23]Kevin Skadron, Mircea R. Stan
Temperature-Aware Microarchitecture. ISCA 2003: 2-13 - [c22]Mircea R. Stan
MTCMOS with outer feedback (MTOF) flip-flops. ISCAS (5) 2003: 429-432 - [c21]Matthew M. Ziegler, Mircea R. Stan
The CMOS/nano interface from a circuits perspective. ISCAS (4) 2003: 904-907 - [e1]Mircea R. Stan, David Garrett, Kazuo Nakajima:
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003. ACM 2003, ISBN 1-58113-677-3 [contents] - 2002
- [j9]Mircea R. Stan
CMOS Circuits with Subvolt Supply Voltages. IEEE Des. Test Comput. 19(2): 34-43 (2002) - [j8]Sriram R. Vangal, Mark A. Anders, Nitin Borkar, Erik Seligman, Venkatesh Govindarajulu, Vasantha Erraguntla, Howard Wilson, Amaresh Pangal, Venkat Veeramachaneni, James W. Tschanz, Yibin Ye, Dinesh Somasekhar, Bradley A. Bloechel, Gregory E. Dermer, Ram K. Krishnamurthy, Krishnamurthy Soumyanath, Sanu Mathew, Siva G. Narendra, Mircea R. Stan
5-GHz 32-bit integer execution core in 130-nm dual-VT CMOS. IEEE J. Solid State Circuits 37(11): 1421-1432 (2002) - [j7]Fatih Hamzaoglu, Yibin Ye, Ali Keshavarzi, Kevin Zhang, Siva G. Narendra, Shekhar Borkar, Mircea R. Stan
Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache. IEEE Trans. Very Large Scale Integr. Syst. 10(2): 91-95 (2002) - [c20]Zhijian Lu, Jason Hein, Marty Humphrey, Mircea R. Stan
Control-theoretic dynamic frequency and voltage scaling for multimedia workloads. CASES 2002: 156-163 - [c19]Mircea R. Stan
The Selective Pull-Up (SP) Noise Immunity Scheme for Dynamic Circuits. DATE 2002: 1106 - [c18]Kevin Skadron
Control-Theoretic Techniques and Thermal-RC Modeling for Accurate and Localized Dynamic Thermal Management. HPCA 2002: 17-28 - [c17]Dharmesh Parikh, Kevin Skadron
Power Issues Related to Branch Prediction. HPCA 2002: 233-244 - [c16]Matthew M. Ziegler, Mircea R. Stan
A Case for CMOS/nano co-design. ICCAD 2002: 348-352 - [c15]Fatih Hamzaoglu, Mircea R. Stan:
Circuit-level techniques to control gate leakage for sub-100nm CMOS. ISLPED 2002: 60-63 - [c14]Yan Zhang, John C. Lach, Kevin Skadron, Mircea R. Stan:
Odd/even bus invert with two-phase transfer for buses with coupling. ISLPED 2002: 80-83 - [c13]Mircea R. Stan
Teaching processor architecture with a VLSI perspective. WCAE 2002: 3 - 2001
- [j6]Mircea R. Stan
Low-power CMOS with subvolt supply voltages. IEEE Trans. Very Large Scale Integr. Syst. 9(2): 394-400 (2001) - [j5]Alvar Dean, David Garrett, Mircea R. Stan
Low Power Design for ASIC Cores. VLSI Design 12(3): 317-331 (2001) - [c12]David Garrett, Mircea R. Stan
A 2.5 Mb/s, 23 mW SOVA traceback chip for turbo decoding applications. ISCAS (4) 2001: 61-64 - [c11]Joshua L. Garrett, Mircea R. Stan
Active threshold compensation circuit for improved performance in cooled CMOS systems. ISCAS (4) 2001: 410-413 - [c10]Matthew M. Ziegler, Mircea Stan
Optimal logarithmic adder structures with a fanout of two for minimizing the area-delay product. ISCAS (2) 2001: 657-660 - 2000
- [c9]A. Forestier, Mircea R. Stan:
Limits to Voltage Scaling from the Low Power Perspective. SBCCI 2000: 365-370
1990 – 1999
- 1999
- [c8]David Garrett, Mircea R. Stan
Challenges in clockgating for a low power ASIC methodology. ISLPED 1999: 176-181 - [c7]Mircea R. Stan:
Optimal Voltages and Sizing for Low Power. VLSI Design 1999: 428-433 - 1998
- [j4]Mircea R. Stan
Long and Fast Up/Down Counters. IEEE Trans. Computers 47(7): 722-735 (1998) - [c6]Mircea R. Stan
Low threshold CMOS circuits with low standby current. ISLPED 1998: 97-99 - [c5]David Garrett, Mircea R. Stan
Low power architecture of the soft-output Viterbi algorithm. ISLPED 1998: 262-267 - 1997
- [j3]Mircea R. Stan
Low-power encodings for global communication in CMOS VLSI. IEEE Trans. Very Large Scale Integr. Syst. 5(4): 444-455 (1997) - [c4]Mircea R. Stan
Synchronous Up/Down Counter with Clock Period Independent of Counter Size. IEEE Symposium on Computer Arithmetic 1997: 274-281 - [c3]David Garrett, Mircea R. Stan
Power reduction techniques for a spread spectrum based correlator. ISLPED 1997: 225-230 - 1996
- [c2]Mircea R. Stan
Two dimensional codes for low power. ISLPED 1996: 335-340 - 1995
- [j2]Mircea R. Stan
Bus-invert coding for low-power I/O. IEEE Trans. Very Large Scale Integr. Syst. 3(1): 49-58 (1995) - [c1]Mircea R. Stan
Coding a terminated bus for low power. Great Lakes Symposium on VLSI 1995: 70-73 - 1994
- [j1]Mircea R. Stan
Analog VLSI for robot path planning. J. VLSI Signal Process. 8(1): 61-73 (1994)
Coauthor Index
[c147] [c146] [c143] [j53] [c137] [c136] [j49] [c128] [c126] [c125] [c124] [j47] [j46] [j44] [c120] [c115] [j43] [j42] [c107] [j37] [c102] [c100] [c99] [c98] [c97] [i2] [j36] [j35] [c94] [c93] [c92] [c91] [i1] [c88] [c87] [c86] [c83] [c81] [c79] [j34] [c69] [j30] [j29] [c56] [c53] [j25] [c51] [j21] [j20] [c41] [j19] [j18] [c36] [c35] [c33] [j17] [j16] [c31] [c30] [c28] [j14] [j13] [j12] [j11] [c24] [c23] [c20] [c18] [c17] [c14] [c13]
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