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IEEE Transactions on Very Large Scale Integration Systems, Volume 31
Volume 31, Number 1, January 2023
- Massimo Alioto:
Opening of the 2023 Editorial Year - This Coda as Prelude of Next TVLSI Cycle With Sustained Growth. 1-3 - Ke Chen
, Yue Gao, Haroon Waris
Approximate Softmax Functions for Energy-Efficient Deep Neural Networks. 4-16 - Morgana Macedo Azevedo da Rosa
AxPPA: Approximate Parallel Prefix Adders. 17-28 - Henry Lopez Davila
Low Routing Complexity Multiframe Pipelined LDPC Decoder Based on a Novel Pseudo Marginalized Min-Sum Algorithm for High Throughput Applications. 29-42 - Syed Mohsin Abbas
List-GRAND: A Practical Way to Achieve Maximum Likelihood Decoding. 43-54 - Kleber Stangherlin
Enhancing Strong PUF Security With Nonmonotonic Response Quantization. 55-64 - Tasnuva Farheen
A Twofold Clock and Voltage-Based Detection Method for Laser Logic State Imaging Attack. 65-78 - Rohith Rajesh, Sumit Jagdish Darak
Hardware-Software Co-Design of Statistical and Deep-Learning Frameworks for Wideband Sensing on Zynq System on Chip. 79-89 - Hongyan Li, Hang Lu
BitXpro: Regularity-Aware Hardware Runtime Pruning for Deep Neural Networks. 90-103 - Aswini K. Samantaray
Power-Efficient VLSI Architecture of a New Class of Dyadic Gabor Wavelets for Medical Image Retrieval. 104-113 - Shubham Jain
A Heterogeneous and Programmable Compute-In-Memory Accelerator Architecture for Analog-AI Using Dense 2-D Mesh. 114-127 - Fujun Bai
A Low-Cost Reduced-Latency DRAM Architecture With Dynamic Reconfiguration of Row Decoder. 128-141 - Zhen Gao
Reliability Evaluation and Fault Tolerance Design for FPGA Implemented Reed Solomon (RS) Erasure Decoders. 142-146 - Meysam Akbari
Implementation of a Multipath Fully Differential OTA in 0.18-μm CMOS Process. 147-151 - Lei Qiu
A High-Speed Low-Noise Comparator With Auxiliary-Inverter-Based Common Mode-Self-Regulation for Low-Supply-Voltage SAR ADCs. 152-156 - Alvaro Cintas Canto
Reliable Architectures for Finite Field Multipliers Using Cyclic Codes on FPGA Utilized in Classic and Post-Quantum Cryptography. 157-161
Volume 31, Number 2, February 2023
- Taehak Kim
NS3K: A 3-nm Nanosheet FET Standard Cell Library Development and its Impact. 163-176 - Eun-Bin Park
Complementary FET (CFET) Standard Cell Design for Low Parasitics and Its Impact on VLSI Prediction at 3-nm Process. 177-187 - Yunbo Huang, Yong Chen
A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fsRMSJitter, -258.7-dB FOM, and -75.17-dBc Reference Spur. 188-198 - Yushen Fu
A 6.0-GS/s Time-Interleaved DAC Using an Asymmetric Current-Tree Summation Network and Differential Clock Timing Calibration. 199-209 - Jun Wang
Fast Estimation of a Statistical Eye Diagram for Nonlinear High-Speed Links Based on the Minimum Required Order of the Multiple Edge Response Method. 210-218 - Yifan Guo
A 60-Mode High-Throughput Parallel-Processing FFT Processor for 5G/4G Applications. 219-232 - Yujia Wang, Jincheng Zhang, Yong Chen
A 4.5-W, 18.5-24.5-GHz GaN Power Amplifier Employing Chebyshev Matching Technique. 233-242 - Qirui Ren, Qiang Huo, Zhisheng Chen, Qi Gao, Yiming Wang, Yiming Yang, Hao Wu, Xiangqu Fu, Xiaoxin Xu, Qing Luo, Jianfeng Gao, Chengying Chen, Xiaojin Zhao, Dengyun Lei, Xinghua Wang, Feng Zhang, Yong Chen, Pui-In Mak:
A Security-Enhanced, Charge-Pump-Free, ISO14443-A-/ISO10373-6-Compliant RFID Tag With 16.2-μW Embedded RRAM and Reconfigurable Strong PUF. 243-252 - Hongbing Tan
Multiple-Mode-Supporting Floating-Point FMA Unit for Deep Learning Processors. 253-266 - Irith Pomeranz
Path Unselection for Path Delay Fault Test Generation. 267-275 - Irith Pomeranz
Diagnostic Test Point Insertion and Test Compaction. 276-285 - Jahyun Koo
Corrections to "Low-Noise Distributed RC Oscillator". 286
Volume 31, Number 3, March 2023
- Yousef Safari
A Robust Integrated Power Delivery Methodology for 3-D ICs. 287-295 - Arjun Chaudhuri
Built-In Self-Test of High-Density and Realistic ILV Layouts in Monolithic 3-D ICs. 296-309 - Chih-Chyau Yang
A 1.6-mW Sparse Deep Learning Accelerator for Speech Separation. 310-319 - Rushik Parmar
Design of DNN-Based Low-Power VLSI Architecture to Classify Atrial Fibrillation for Wearable Devices. 320-330 - Honghao Zheng
Enabling a New Methodology of Neural Coding: Multiplexing Temporal Encoding in Neuromorphic Computing. 331-342 - Yung-Chuan Su, Shi-Yu Huang
A Process-Adaptive Cell-Based Cyclic Time-to-Digital Converter Using One-Way Varactor Cells. 343-354 - Ananda Y. R.
A MOS-DTMOS Implementation of Floating Memristor Emulator for High-Frequency Applications. 355-368 - Nakisa Shams
Blocker-Tolerant Inductor-Less Harmonic Selection Wideband Receiver Front-End for 5G Applications. 369-381 - Stefan Brennsteiner
LAMANet: A Real-Time, Machine Learning-Enhanced Approximate Message Passing Detector for Massive MIMO. 382-395 - Peng Jing
VLSI Design of a High-Performance Multicontext MQ Arithmetic Coder. 396-400 - Dionysios Filippas
Streaming Dilated Convolution Engine. 401-405 - Song-Nien Tang
Area-Efficient Parallel Multiplication Units for CNN Accelerators With Output Channel Parallelization. 406-410
Volume 31, Number 4, April 2023
- Stephan Eggersglüß
A New Static Compaction of Deterministic Test Sets. 411-420 - Irith Pomeranz
Sharing of Compressed Tests Among Logic Blocks. 421-430 - Abdullah Ibn Abbas
A Power-Proportional, Dual-Bandwidth, and Constant-Delay Receiver Front-End for Energy-Efficient Dual-Rate Optical Links. 431-441 - Wu Zhou
Energy-Efficient Multiple Network-on-Chip Architecture With Bandwidth Expansion. 442-455 - Jie Chen
Scalable Hierarchical Instruction Cache for Ultralow-Power Processors Clusters. 456-469 - Wenhao Sun, Deng Liu, Zhiwei Zou, Wendi Sun, Song Chen
Sense: Model-Hardware Codesign for Accelerating Sparse CNNs on Systolic Arrays. 470-483 - Ming Ling
Vina-FPGA: A Hardware-Accelerated Molecular Docking Tool With Fixed-Point Quantization and Low-Level Parallelism. 484-497 - Jones William Goebel
A High-Throughput Hardware Design for the AV1 Decoder Intraprediction. 498-511 - Haofan Ding
A 10-Gb/s Inductorless Low-Power TIA With a 400-fF Low-Speed Avalanche Photodiode Realized in CMOS Process. 512-521 - Zhiting Lin
High Restore Yield NVSRAM Structures With Dual Complementary RRAM Devices for High-Speed Applications. 522-531 - Aika Kamei
A Variation-Aware MTJ Store Energy Estimation Model for Edge Devices With Verify-and-Retryable Nonvolatile Flip-Flops. 532-542 - Shivani Bathla
A Framework for Reliability Analysis of Combinational Circuits Using Approximate Bayesian Inference. 543-554 - Ayesha Siddique, Khaza Anuarul Hoque
Exposing Reliability Degradation and Mitigation in Approximate DNNs Under Permanent Faults. 555-566 - Yang Ge
A Single-TSV and Single-DCDL Approach for Skew Compensation of Multi-Dies Clock Synchronization in 3-D-ICs. 567-577 - Youngkwang Lee
TSV Built-In Self-Repair Architecture for Improving the Yield and Reliability of HBM. 578-590 - Sangwoo Han
Page Type-Aware Data Migration Technique for Read Disturb Management of NAND Flash Memory. 591-595 - Pengzhou He
COPMA: Compact and Optimized Polynomial Multiplier Accelerator for High-Performance Implementation of LWR-Based PQC. 596-600 - Irith Pomeranz
Test Data Compression for Transparent-Scan Sequences. 601-605 - Kexu Chen
An Improved MOS Self-Biased Ring Amplifier and Modified Auto-Zeroing Scheme. 606-610
Volume 31, Number 5, May 2023
- Eunsol Jeong
Eliminating Minimum Implant Area Violations With Design Quality Preservation. 611-621 - Kwangmin Kim
A Speculative Divide-and-Conquer Optimization Method for Large Analog/Mixed-Signal Circuits: A High-Speed FFE SST Transmitter Example. 622-635 - Giuseppe E. Biccario
A 5-V Switch for Analog Multiplexers With 2.5-V Transistors in 28-nm CMOS Technology. 636-643 - Nakisa Shams
An OOK and Binary FSK Reconfigurable Dual-Band Noncoherent IR-UWB Receiver Supporting Ternary Signaling. 644-657 - Zhijian Hao
A Reconfigurable Multiple Transform Selection Architecture for VVC. 658-669 - Sumit K. Mandal
Fast Performance Analysis for NoCs With Weighted Round-Robin Arbitration and Finite Buffers. 670-683 - Yuqi Wang
A Reliable and High-Speed 6T Compute-SRAM Design With Dual-Split-VDD Assist and Bitline Leakage Compensation. 684-695 - Yangyang Chen
An Efficient Massive MIMO Detector Based on Approximate Expectation Propagation. 696-700 - Jihwan Park
Energy-Efficient Wide-Range Level Shifter With a Logic Error Detection Circuit. 701-705 - Zisong Wang
Low-Power Redundant-Transition-Free TSPC Dual-Edge-Triggering Flip-Flop Using Single-Transistor-Clocked Buffer. 706-710
Volume 31, Number 6, June 2023
- Tobias Kilian
Performance Screening Using Functional Path Ring Oscillators. 711-724 - SatyaJaswanth Badri
An Efficient NVM-Based Architecture for Intermittent Computing Under Energy Constraints. 725-737 - Baoting Li, Hang Wang
ACBN: Approximate Calculated Batch Normalization for Efficient DNN On-Device Training Processor. 738-748 - Wonjae Lee
A Real-Time Object Detection Processor With xnor-Based Variable-Precision Computing Unit. 749-761 - Pedro Sartori Locatelli
Time-Domain Multiply-Accumulate Unit. 762-775 - Zhiting Lin
A Fully Digital SRAM-Based Four-Layer In-Memory Computing Unit Achieving Multiplication Operations and Results Store. 776-788 - Ramesh Sambangi
Application Mapping Onto Manycore Processor Architectures Using Active Search Framework. 789-801 - An-Jung Huang, Jo-Hsuan Hung, Tian-Sheuan Chang
Memory Bandwidth Efficient Design for Super-Resolution Accelerators With Structure Adaptive Fusion and Channel-Aware Addressing. 802-811 - Levent Aksoy
Hybrid Protection of Digital FIR Filters. 812-825 - Anirban Sengupta
Robust Security of Hardware Accelerators Using Protein Molecular Biometric Signature and Facial Biometric Encryption Key. 826-839 - Eric Hunt-Schroeder
12-nm Stable Pre-Amplifier Physical Unclonable Function With Self-Destruct Capability. 840-850 - Woojung Kim
A 5.4-Gb/s, 0.57-pJ/bit, Single-Loop Referenceless CDR With an Unlimited Bilateral Frequency Detection Scheme. 851-860 - Debao Wei
Edge Word-Line Reliability Problem in 3-D NAND Flash Memory: Observations, Analysis, and Solutions. 861-873 - Malek Souilem
Signal and Power Integrity IO Buffer Modeling Under Separate Power and Ground Supply Voltage Variation of the Input and Output Stages. 874-886 - Zhifei Lu
A Novel Two-Stage Timing Mismatch Calibration Technique for Time-Interleaved ADCs. 887-891 - Yazheng Tu
LEAP: Lightweight and Efficient Accelerator for Sparse Polynomial Multiplication of HQC. 892-896 - Zhuolun Wu
A High-Performance Dual-Context MQ Encoder Architecture Based on Extended Lookup Table. 897-901 - Zhe Yu, Yuhua Liang
A Time-Domain Reconfigurable Second-Order Noise Shaping ADC With Single Fan-Out Gated Delay Cells. 902-905 - Tao Li
Corrections to "Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator". 906
Volume 31, Number 7, July 2023
- Chandan Kumar Jha
Single Exact Single Approximate Adders and Single Exact Dual Approximate Adders. 907-916 - Marzieh Vaeztourshizi
Efficient Error Estimation for High-Level Design Space Exploration of Approximate Computing Systems. 917-930 - Haoran Geng
QPA: A Quantization-Aware Piecewise Polynomial Approximation Methodology for Hardware-Efficient Implementations. 931-944 - Steven Colleman
COAC: Cross-Layer Optimization of Accelerator Configurability for Efficient CNN Processing. 945-958 - Bharat Bhushan Upadhyay
VLSI Design of Saturation-Based Image Dehazing Algorithm. 959-968 - Jonathan Cruz
TVF: A Metric for Quantifying Vulnerability Against Hardware Trojan Attacks. 969-979 - Shaopu Han
RISC-V-Based Evaluation and Strategy Exploration of MRAM Triple-Level Hybrid Cache Systems. 980-992 - Sahibia Kaur Vohra
Full CMOS Circuit for Brain-Inspired Associative Memory With On-Chip Trainable Memristive STDP Synapse. 993-1003 - Lianxi Liu
A 0.4-V Startup, Dead-Zone-Free, Monolithic Four-Mode Synchronous Buck-Boost Converter. 1004-1013 - Namik K. Kocaman, Michael M. Green
Asynchronous Sampling-Based Hybrid Equalizer. 1014-1025 - Syed Asrar ul Haq
Deep Neural Network Augmented Wireless Channel Estimation for Preamble-Based OFDM PHY on Zynq System on Chip. 1026-1038 - Xin Chen
Low-Overhead Triple-Node-Upset-Tolerant Latch Design in 28-nm CMOS. 1039-1050 - Jafar Vafaei
X-Rel: Energy-Efficient and Low-Overhead Approximate Reliability Framework for Error-Tolerant Applications Deployed in Critical Systems. 1051-1064 - Rakesh Varma Rena
0.4-1 GHz Subsampling Mixer-First RF Front-End With 50-dB HRR, +10-dBm IB-IIP3 in 65-nm CMOS. 1065-1077 - Tao Li
Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator. 1078-1082 - Komala Krishna, Nandakumar Nambath
Cascode Cross-Coupled Stage High-Speed Dynamic Comparator in 65 nm CMOS. 1083-1086
Volume 31, Number 8, August 2023
- Mircea R. Stan
Editorial New Beginnings for IEEE TVLSI. 1087-1113 - Kun-Chih Chen
Adaptive Machine Learning-Based Proactive Thermal Management for NoC Systems. 1114-1127 - Ganesh Gore
A Scalable and Area-Efficient Configuration Circuitry for Semi-Custom FPGA Design. 1128-1139 - Yunyou Pu
A Tri-Mode Reconfigurable Receiver for GNSS/NB-IoT/BLE With 68-dB HR3 and 60-dB IMRR in 28-nm CMOS. 1140-1152 - Jianfei Wang
TCPM: A Reconfigurable and Efficient Toom-Cook-Based Polynomial Multiplier Over Rings Using a Novel Compressed Postprocessing Algorithm. 1153-1166 - Anu Verma
An Efficient Scaling-Free Folded Hyperbolic CORDIC Design Using a Novel Low-Complexity Power-of-2 Taylor Series Approximation. 1167-1177 - Jindong Li
FireFly: A High-Throughput Hardware Accelerator for Spiking Neural Networks With Efficient DSP and Memory Optimization. 1178-1191 - Medien Zeghid
Speed/Area-Efficient ECC Processor Implementation Over GF(2m) on FPGA via Novel Algorithm-Architecture Co-Design. 1192-1203 - Aurélien Alacchi
Smart-Redundancy With In Memory ECC Checking: Low-Power SEE-Resistant FPGA Architectures. 1204-1213 - Felipe G. A. e Silva, Alan Cadore Pinheiro, Jarbas A. N. Silveira
A Triple Burst Error Correction Based on Region Selection Code. 1214-1222 - Shrihari Sridharan
X-Former: In-Memory Acceleration of Transformers. 1223-1233 - Zhuojun Chen
PUF-CIM: SRAM-Based Compute-In-Memory With Zero Bit-Error-Rate Physical Unclonable Function for Lightweight Secure Edge Computing. 1234-1247 - Yuchen Wei
A 0.0043-mm2 0.085-μW/MHz Relaxation Oscillator Using Charge-Prestored Asymmetric Swings R-RC Network. 1248-1252 - Alexander Choo Chia Chun
A High-Performance Dual-Topology CMOS Rectifier With 19.5-dB Power Dynamic Range for RF-Based Hybrid Energy Harvesting. 1253-1257
Volume 31, Number 9, September 2023
- Irith Pomeranz
Storage-Based Logic Built-In Self-Test With Partitioned Deterministic Compressed Tests. 1259-1268 - Aruna Jayasena
TVLA*: Test Vector Leakage Assessment on Hardware Implementations of Asymmetric Cryptography Algorithms. 1269-1279 - Divya Praneetha Ravipati
Performance and Energy Studies on NC-FinFET Cache-Based Systems With FN-McPAT. 1280-1293 - Dongwei Zou
FPGA-Based Configurable and Highly Flexible PAM4 SerDes Simulation System. 1294-1307 - Jai-Ming Lin
Multilevel Fixed-Outline Component Placement and Graph-Based Ball Assignment for System in Package. 1308-1319 - Clara Nieto-Taladriz
Automated In-Situ Monitoring for Variability-Resilient and Energy-Efficient Digital Circuits Demonstrated on a Viterbi Decoder in 22-nm CMOS. 1320-1329 - Yu-Jie Chou, Hsiao-Chin Chen
Design and Analysis of Sub-Sampling Phase-Locked Loop for Quantum Computing. 1330-1338 - Nurzhan Zhuldassov
Thermal Optimization of Hybrid Cryogenic Computing Systems. 1339-1346 - Marcel Khalifa
ClaPIM: Scalable Sequence Classification Using Processing-in-Memory. 1347-1357 - Junyeong Bae, Junseok Oh, Myoung Jin Lee
Timestamp-Based Secure Shield Architecture for Detecting Invasive Attacks. 1358-1367 - Anil Kali
Low-Complexity Distributed Arithmetic-Based Architecture for Inner-Product of Variable Vectors. 1368-1376 - Alexander J. Leigh
A Resource-Efficient and High-Accuracy CORDIC-Based Digital Implementation of the Hodgkin-Huxley Neuron. 1377-1388 - Loai G. Salem
Analysis and Optimization of Switched-Capacitor Piezoelectric Energy Harvesting Interface Circuits. 1389-1402 - Young-Ha Hwang
An Area/Power-Efficient ΔΣ Modulator Based on Dynamic-Boost Inverter for Multichannel Sensor Applications. 1403-1412 - Peng Cao
Efficient and Accurate ECO Leakage Optimization Framework With GNN and Bidirectional LSTM. 1413-1424 - Wei-Tse Hung, Yu-Guang Chen
DRC Violation Prediction After Global Route Through Convolutional Neural Network. 1425-1438 - Yongqiang Zhang
An Energy-Efficient Binary-Interfaced Stochastic Multiplier Using Parallel Datapaths. 1439-1443 - Andrea Ballo
A 0.3-V 8.5-μ a Bulk-Driven OTA. 1444-1448 - Rongrong She
A New ACD-OMP Accelerator With Clustered Computing Look-Ahead. 1449-1453 - Zhongzhen Tong
In-Memory Transposable Multibit Multiplication Based on Diagonal Symmetry Weight Block. 1454-1458
Volume 31, Number 10, October 2023
- Jitendra Bhandari
Not All Fabrics Are Created Equal: Exploring eFPGA Parameters for IP Redaction. 1459-1471 - Chen Yang
A High-Throughput and Flexible Architecture Based on a Reconfigurable Mixed-Radix FFT With Twiddle Factor Compression and Conflict-Free Access. 1472-1485 - Jie Xiao
Estimating Redundancy-Reliability of CNNs Based on Strip-Median Attributes. 1486-1496 - Mark Keran
An Analytic RLC Model for Coupled Interconnects Which Uses a Numerical Inverse Laplace Transform. 1497-1508 - Madhan Thirumoorthi
Novel Formulations of M-Term Overlap-Free Karatsuba Binary Polynomial Multipliers and Their Hardware Implementations. 1509-1522 - Zahra Azad
RISE: RISC-V SoC for En/Decryption Acceleration on the Edge for Homomorphic Encryption. 1523-1536 - Yishuo Meng
An Efficient CNN Accelerator Achieving High PE Utilization Using a Dense-/Sparse-Aware Redundancy Reduction Method and Data-Index Decoupling Workflow. 1537-1550 - Pengzhou He
KINA: Karatsuba Initiated Novel Accelerator for Ring-Binary-LWE (RBLWE)-Based Post-Quantum Cryptography. 1551-1564 - Bayartulga Ishdorj
Spin-Transfer-Torque Magnetic-Tunnel-Junction-Based Low-Power Nonvolatile Flip-Flop Designs in the Subthreshold Voltage Region. 1565-1577 - Siqing Fu
RHS-TRNG: A Resilient High-Speed True Random Number Generator Based on STT-MTJ Device. 1578-1591 - Wantong Li
H3DAtten: Heterogeneous 3-D Integrated Hybrid Analog and Digital Compute-in-Memory Accelerator for Vision Transformer Self-Attention. 1592-1602 - Gauthaman Murali
On Continuing DNN Accelerator Architecture Scaling Using Tightly Coupled Compute-on-Memory 3-D ICs. 1603-1613 - Lin Sun, Zhenwei Zhang, Lili Lang
An Adaptive and Universal Timing Mismatch Estimation Method for TIADCs. 1614-1618 - Kishore Kumar Pakkirisami Churchill
A Reconfigurable CMOS Stack Rectifier With 22.8-dB Dynamic Range Achieving 47.91% Peak PCE for IoT/WSN Application. 1619-1623 - Meysam Akbari
A Rail-to-Rail Transconductance Amplifier Based on Current Generator Circuits. 1624-1628 - Hee Sung Lee
Low-Phase-Noise 20-GHz Phase-Locked Loop Using Harmonic-Tuned VCO Assisting With gm-Boosting Technique. 1629-1633 - Elamana Marakkadath Dalin, S. M. Rezaul Hasan
A Low Phase-Lag Self-Powered SECE Interface Circuit for Pressure-Type Piezoelectric Energy-Harvesting Compatible With COTS Pressure Sensors. 1634-1638
Volume 31, Number 11, November 2023
- Wenbo Guan
A Novel Thermal-Aware Floorplanning and TSV Assignment With Game Theory for Fixed-Outline 3-D ICs. 1639-1652 - Wei Xiong
Miniaturization Strategy for Directional Couplers Based on Through-Silicon Via Insertion and Neuro-Transfer Function Modeling Method. 1653-1664 - Hamed Aminzadeh
Hybrid Cascode Frequency Compensation for Four-Stage OTAs Driving a Wide Range of CL. 1665-1674 - R. Malmir, M. B. Ghaznavi-Ghoushchi
Design and Analysis of an Ultralow-Voltage Complementary Fold-Interleaved Multiple-Tail Current Mode Logic. 1675-1685 - Apostolos Stefanidis
Synthesis of Approximate Parallel-Prefix Adders. 1686-1699 - Rui Xiao
A Low-Power In-Memory Multiplication and Accumulation Array With Modified Radix-4 Input and Canonical Signed Digit Weights. 1700-1712 - Bruno Sá
CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space Exploration. 1713-1726 - Jianwang Zhai
Microarchitecture Design Space Exploration via Pareto-Driven Active Learning. 1727-1739 - Johannes Bund
PALS: Distributed Gradient Clocking on Chip. 1740-1753 - Irith Pomeranz
Dummy Faulty Units for Reduced Fail Data Volume From Logic Faults. 1754-1762 - Xinghua Xue
Exploring Winograd Convolution for Cost-Effective Neural Network Fault Tolerance. 1763-1773 - Trio Adiono
Fast and Scalable Multicore YOLOv3-Tiny Accelerator Using Input Stationary Systolic Architecture. 1774-1787 - Haikuo Shao
An Efficient Training Accelerator for Transformers With Hardware-Algorithm Co-Optimization. 1788-1801 - Vaibhav Venugopal Rao
Hidden Costs of Analog Deobfuscation Attacks. 1802-1815 - Prachi Kashikar
Lossless Neural Network Model Compression Through Exponent Sharing. 1816-1825 - Jianwei Xue
SFANC: Scalable and Flexible Architecture for Neuromorphic Computing. 1826-1838 - Xiangrong Huang
A 24-30-GHz Four-Element Phased Array Transceiver With Low Insertion Loss Compact T/R Switch and Bidirectional Phase Shifter for 5G Communication. 1839-1851 - Shao-I Chu
An Efficient Hard-Detection GRAND Decoder for Systematic Linear Block Codes. 1852-1864 - Jianjun Luo, Hailuan Liu
High-Density NVMe SSD With DRAM-Less eRAID Architecture. 1865-1869 - Yi Shen
An 8-bit 1.5-GS/s Two-Step SAR ADC With Embedded Interstage Gain. 1870-1873 - Jordi Fornt
An Energy-Efficient GeMM-Based Convolution Accelerator With On-the-Fly im2col. 1874-1878
Volume 31, Number 12, December 2023
- Mircea R. Stan:
Editorial Rolling Out the IEEE TVLSI EDICS. 1879-1881 - Wenbo Guan
Thermal-Aware Fixed-Outline 3-D IC Floorplanning: An End-to-End Learning-Based Approach. 1882-1895 - Sankatali Venkateswarlu
Impact of 3-D Integration on Thermal Performance of RISC-V MemPool Multicore SOC. 1896-1904 - Wenbo Guan
ATT-TA: A Cooperative Multiagent Deep Reinforcement Learning Approach for TSV Assignment in 3-D ICs. 1905-1917 - Carlos Manuel Domínguez-Matas
Behavioral Model for High-Speed SAR ADCs With On-Chip References. 1918-1930 - Heng Zhang
A 1-GS/s 12-bit Single-Channel Pipelined ADC in 28-nm CMOS With Input-Split Fully Differential Ring Amplifier. 1931-1938 - Pai-Hsiang Hsu, Yueh-Ru Lee
A Low-Noise Area-Efficient Column-Parallel ADC With an Input Triplet for a 120-dB High Dynamic Range CMOS Image Sensor. 1939-1949 - Mahyar Safiallah
A Current-Adjusting Auto-Zeroing Technique for DC-Offset and Flicker-Noise Cancellation. 1950-1959 - Cheng-Yen Lee
A Digital Low Dropout (LDO) Voltage Regulator Using Pseudoflash Transistors. 1960-1969 - Ranran Zhou
A 55-nm Three-Stage Operational Transconductance Amplifier With Single Cascode Miller Compensation for Large Capacitive Loads. 1970-1979 - Wenzhe Zhao
HIPU: A Hybrid Intelligent Processing Unit With Fine-Grained ISA for Real-Time Deep Neural Network Inference Applications. 1980-1993 - Pai-Yu Tan
A 40-nm 1.89-pJ/SOP Scalable Convolutional Spiking Neural Network Learning Core With On-Chip Spatiotemporal Back-Propagation. 1994-2007 - Meenali Janveja
An Optimized Low-Power VLSI Architecture for ECG/VCG Data Compression for IoHT Wearable Device Application. 2008-2015 - Ngo-Doanh Nguyen
Power-Aware Neuromorphic Architecture With Partial Voltage Scaling 3-D Stacking Synaptic Memory. 2016-2029 - Yicong Zhang
TensorCache: Reconstructing Memory Architecture With SRAM-Based In-Cache Computing for Efficient Tensor Computations in GPGPUs. 2030-2043 - Hongyang Hu
A 40-nm SONOS Digital CIM Using Simplified LUT Multiplier and Continuous Sample-Hold Sense Amplifier for AI Edge Inference. 2044-2052 - Ashvinikumar Dongre
ADC-Less Reprogrammable RRAM Array Architecture for In-Memory Computing. 2053-2060 - Dongyu Xu
RMC_NoC: A Reliable On-Chip Network Architecture With Reconfigurable Multifunctional Channel. 2061-2074 - Zeinab Seifoori
PERA: Power-Efficient Routing Architecture for SRAM-Based FPGAs in Dark Silicon Era. 2075-2088 - Jiuxin Gong
A Reusable and Efficient Architecture for QC-LDPC Encoder With Less Expansion Factors. 2089-2101 - Nan Zhang, Jinghan Feng
Parallel Doubly Fed Symbol Timing Recovery Algorithm and FPGA Implementation for Burst Broadband Satellite Access. 2102-2111 - Panagiota Papavramidou, Michael Nicolaidis
Reducing Power Dissipation in Memory Repair for High Fault Rates. 2112-2125 - Xinghua Xue
Soft Error Reliability Analysis of Vision Transformers. 2126-2136 - Sungju Ryu
Binaryware: A High-Performance Digital Hardware Accelerator for Binary Neural Networks. 2137-2141 - Yuyang Li
A 5-mm2, 4.7-μW Convolutional Neural Network Layer Accelerator for Miniature Systems. 2142-2146 - Xin Zhao
An 8-bit 1.5-GS/s Voltage-Time Hybrid Two-Step ADC With Cross-Coupled Linearized VTC. 2147-2151 - Seongun Bae
A Temperature Compensated Ring Oscillator With LC-Based Period Error Detection. 2152-2156
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