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ICCAD 2017: Irvine, CA, USA
- Sri Parameswaran:
2017 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2017, Irvine, CA, USA, November 13-16, 2017. IEEE 2017, ISBN 978-1-5386-3093-8 - Sourav Das, Srinivasan Gopal
, Deukhyoun Heo, Partha Pratim Pande:
Energy-efficient and robust 3D NoCs with contactless vertical links (Invited paper). 1-6 - Krysta M. Svore:
Keynote addresses: Quantum computing: Revolutionizing computation through quantum mechanics. 1-2 - Mohammad Arjomand, Amin Jadidi, Mahmut T. Kandemir, Chita R. Das:
Leveraging value locality for efficient design of a hybrid cache in multicore processors. 1-8 - Yun Liang, Xiuhong Li, Xiaolong Xie:
Exploring cache bypassing and partitioning for multi-tasking on GPUs. 9-16 - Ming-Chang Yang, Yuan-Hao Chang
Virtual persistent cache: Remedy the long latency behavior of host-aware shingled magnetic recording drives. 17-24 - Yeseong Kim, Mohsen Imani, Tajana Rosing:
ORCHARD: Visual object recognition accelerator based on approximate in-memory processing. 25-32 - Mohamed El Massad, Siddharth Garg, Mahesh Tripunitara:
Reverse engineering camouflaged sequential circuits without scan access. 33-40 - Satwik Patnaik
Obfuscating the interconnects: Low-cost and resilient full-chip layout camouflaging. 41-48 - Hai Zhou, Ruifeng Jiang, Shuyu Kong:
CycSAT: SAT-based attack on cyclic logic encryptions. 49-56 - Shahrzad Keshavarz, Daniel E. Holcomb:
Threshold-based obfuscated keys with quantifiable security against invasive readout. 57-64 - Yen-Yi Wu, Yao-Wen Chang:
Mixed-cell-height detailed placement considering complex minimum-implant-area constraints. 65-72 - Sheng-Wei Yang, Yao-Wen Chang, Tung-Chieh Chen:
Blockage-aware terminal propagation for placement wirelength minimization. 73-80 - Yuzhe Ma, Jhih-Rong Gao, Jian Kuang, Jin Miao, Bei Yu:
A unified framework for simultaneous layout decomposition and mask optimization. 81-88 - Luca Mattii, Dragomir Milojevic
IR-drop aware Design & technology co-optimization for N5 node with different device and cell height options. 89-94 - Jianwen Li, Shufang Zhu
Safety model checking with complementary approximations. 95-100 - Pouya Taatizadeh, Nicola Nicolici:
An automated SAT-based method for the design of on-chip bit-flip detectors. 101-108 - Nian-Ze Lee
Sequential engineering change order under retiming and resynthesis. 109-116 - Denny C.-Y. Wu, Pin-Ru Jhao, Charles H.-P. Wen
Accelerating functional timing analysis with encoding duplication removal and redundant state propagation. 117-122 - Amit Kumar, Cody Scarborough, Ali E. Yilmaz, Michael Orshansky:
Efficient simulation of EM side-channel attack resilience. 123-130 - Yannan Liu, Lingxiao Wei, Bo Luo, Qiang Xu
Fault injection attack on deep neural network. 131-138 - Zhen Hang Jiang, Yunsi Fei
A novel cache bank timing attack. 139-146 - Armaiti Ardeshiricham, Wei Hu, Ryan Kastner
Clepsydra: Modeling timing flows in hardware designs. 147-154 - Karthik V. Aadithya, Eric R. Keiter
DAGSENS: Directed acyclic graph based direct and adjoint transient sensitivity analysis for event-driven objective functions. 155-162 - Xinyuan Wang, Hao Zhuang, Chung-Kuan Cheng:
Exploring the exponential integrators with Krylov subspace algorithms for nonlinear circuit simulation. 163-168 - Xiaoyi Wang, Yan Yan, Jian He, Sheldon X.-D. Tan, Chase Cook, Shengqi Yang:
Fast physics-based electromigration analysis for multi-branch interconnect trees. 169-176 - Amith Kaushal Rao, Haibo Zeng:
Online message delay prediction for model predictive control over controller area network. 177-184 - Maral Amir, Tony Givargis:
Hybrid state machine model for fast model predictive control: Application to path tracking. 185-192 - Korosh Vatanparvar, Mohammad Abdullah Al Faruque
ACQUA: Adaptive and cooperative quality-aware control for automotive cyber-physical systems. 193-200 - Dandan Li, Shuzhen Yao, Senzhang Wang, Ying Wang:
Cross-program design space exploration by ensemble transfer learning. 201-208 - Adam M. Izraelevitz, Jack Koenig, Patrick Li, Richard Lin, Angie Wang, Albert Magyar, Donggyu Kim, Colin Schmidt, Chick Markley, Jim Lawson, Jonathan Bachrach:
Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations. 209-216 - Yao Xiao, Yuankun Xue, Shahin Nazarian, Paul Bogdan:
A load balancing inspired optimization framework for exascale multicore systems: A complex networks approach. 217-224 - Rotem Ben Hur, Nimrod Wald, Nishil Talati, Shahar Kvatinsky:
Simple magic: Synthesis and in-memory Mapping of logic execution for memristor-aided logic. 225-232 - Arighna Deb, Robert Wille, Rolf Drechsler
Dedicated synthesis for MZI-based optical circuits based on AND-inverter graphs. 233-238 - Kuo-Hao Wu, Shao-Yun Fang:
Simultaneous template assignment and layout decomposition using multiple bcp materials in DSA-MP lithography. 239-244 - Liang Chang
PRESCOTT: Preset-based cross-point architecture for spin-orbit-torque magnetic random access memory. 245-252 - Mohammad Khavari Tavana, David R. Kaeli:
Cost-effective write disturbance mitigation techniques for advancing PCM density. 253-260 - Wen Wen
Speeding up crossbar resistive memory by exploiting in-memory data patterns. 261-267 - Hengyu Zhao, Linuo Xue, Ping Chi, Jishen Zhao:
Approximate image storage with multi-level cell STT-MRAM main memory. 268-275 - Tao Luo
A novel two-stage modular multiplier based on racetrack memory for asymmetric cryptography. 276-282 - Ren-Shuo Liu, Yun-Sheng Chang, Chih-Wen Hung:
VST: A virtual stress testing framework for discovering bugs in SSD flash-translation layers. 283-290 - Jiachen Mao, Zhuwei Qin, Zirui Xu, Kent W. Nixon, Xiang Chen, Hai Li, Yiran Chen:
AdaLearner: An adaptive distributed mobile learning system for neural networks. 291-296 - Moslem Didehban, Aviral Shrivastava
NEMESIS: A software approach for computing in presence of soft errors. 297-304 - Matina Maria Trompouki
An open benchmark implementation for multi-CPU multi-GPU pedestrian detection in automotive systems. 305-312 - Lang Feng, Yujie Wang, Jiang Hu, Wai-Kei Mak, Jeyavijayan Rajendran:
Making split fabrication synergistically secure and manufacturable. 313-320 - Lang Feng, Yujie Wang, Jiang Hu, Wai-Kei Mak, Jeyavijayan Rajendran:
Making split fabrication synergistically secure and manufacturable. 321-328 - Abhrajit Sengupta, Satwik Patnaik
Rethinking split manufacturing: An information-theoretic approach with secure layout techniques. 329-326 - Ankur Sharma, David G. Chinnery
Rapid gate sizing with fewer iterations of Lagrangian Relaxation. 337-343 - Gai Liu, Zhiru Zhang
Statistically certified approximate logic synthesis. 344-351 - Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon, Janet Olson, Robert K. Brayton, Giovanni De Micheli:
Enabling exact delay synthesis. 352-359 - Ramin Fallahzadeh, Parastoo Alinia, Hassan Ghasemzadeh:
Learn-on-the-go: Autonomous cross-subject context learning for internet-of-things applications. 360-367 - Ganapati Bhat, Jaehyun Park
Near-optimal energy allocation for self-powered wearable systems. 368-375 - Zahra Ghodsi, Siddharth Garg, Ramesh Karri
Optimal checkpointing for secure intermittently-powered IoT devices. 376-383 - Shaza Zeitouni, Ghada Dessouky, Orlando Arias, Dean Sullivan, Ahmad Ibrahim, Yier Jin
ATRIUM: Runtime attestation resilient under memory attacks. 384-391 - Jesse Elwell, Dmitry Evtyushkin, Dmitry Ponomarev, Nael B. Abu-Ghazaleh
Hardening extended memory access control schemes with self-verified address spaces. 392-399 - Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Daniel Große
Early SoC security validation by VP-based static information flow analysis. 400-407 - Norman Kluge, Ralf Wollowski:
Data path optimisation and delay matching for asynchronous bundled-data balsa circuits. 408-415 - Milan Ceska
Approximating complex arithmetic circuits with formal error guarantees: 32-bit multipliers accomplished. 416-423 - Cunxi Yu, Mihir Choudhury, Andrew Sullivan, Maciej J. Ciesielski:
Advanced datapath synthesis using graph isomorphism. 424-429 - Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang, Bingsheng He
COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications. 430-437 - Ye Tian, Ting Wang, Qian Zhang, Qiang Xu
ApproxLUT: A novel approximate lookup table-based accelerator. 438-443 - Mingze Gao, Gang Qu:
Energy efficient runtime approximate computing on data flow graphs. 444-449 - Tao Liu, Zihao Liu, Fuhong Lin, Yier Jin
MT-spike: A multilayer time-based spiking neuromorphic architecture with temporal error backpropagation. 450-457 - Siyu Liao, Zhe Li, Xue Lin, Qinru Qiu, Yanzhi Wang, Bo Yuan:
Energy-efficient, high-performance, highly-compressed deep neural network design using block-circulant matrices. 458-465 - Zahi Moudallal, Farid N. Najm:
Power scheduling with active power grids. 466-473 - Bi Wu
Thermosiphon: A thermal aware NUCA architecture for write energy reduction of the STT-MRAM based LLCs. 474-481 - Hong-Wen Chiou, Yu-Min Lee, Hsuan-Hsuan Hsiao, Liang-Chia Cheng:
Thermal modeling and design on smartphones with heat pipe cooling technique. 482-489 - Yi-Chung Chen, Scott Ladenheim, Harry Kalargaris, Milan Mihajlovic, Vasilis F. Pavlidis:
Computationally efficient standard-cell FEM-based thermal analysis. 490-495 - Szu-To Chen, Yao-Wen Chang, Tung-Chieh Chen:
An integrated-spreading-based macro-refining algorithm for large-scale mixed-size circuit designs. 496-503 - Chin-Hao Chang, Yao-Wen Chang, Tung-Chieh Chen:
A novel damped-wave framework for macro placement. 504-511 - Mingyu Woo
GRASP based metaheuristics for layout pattern classification. 512-518 - Yun-Chih Kuo, Chau-Chin Huang, Shih-Chun Chen, Chun-Han Chiang, Yao-Wen Chang, Sy-Yen Kuo
Clock-aware placement for large-scale heterogeneous FPGAs. 519-526 - Yue Zha
RRAM-based reconfigurable in-memory computing architecture with hybrid routing. 527-532 - Aayush Ankit, Abhronil Sengupta, Kaushik Roy:
TraNNsformer: Neural network transformation for memristive crossbar based neuromorphic system design. 533-540 - Bonan Yan, Jianhua Joshua Yang
A closed-loop design to enhance weight stability of memristor based neural network chips. 541-548 - Farnood Merrikh-Bayat, Mirko Prezioso, Bhaswar Chakrabarti, Irina Kataeva, Dmitri B. Strukov
Memristor-based perceptron classifier: Increasing complexity and coping with imperfect hardware. 549-554 - Dongyoun Yi, Taewhan Kim:
Switch cell optimization of power-gated modern system-on-chips. 555-560 - Ting-Chou Lin, Chia-Chih Chi, Yao-Wen Chang:
Redistribution layer routing for wafer-level integrated fan-out package-on-packages. 561-568 - Gengjie Chen, Peishan Tu, Evangeline F. Y. Young:
SALT: Provably good routing topology by a novel steiner shallow-light tree algorithm. 569-576 - Minghua Shen, Guojie Luo, Nong Xiao:
A coordinated synchronous and asynchronous parallel routing approach for FPGAs. 577-584 - Hari Cherupalli, John Sartori:
Scalable N-worst algorithms for dynamic timing and activity analysis. 585-592 - Mohammad Fawaz, Farid N. Najm:
Power grid verification under transient constraints. 593-600 - Zhiqiang Zhao, Yongyu Wang, Zhuo Feng:
SAMG: Sparsified graph-theoretic algebraic multigrid for solving large symmetric diagonally dominant (SDD) matrices. 601-606 - Guo-Gin Fan, Mark Po-Hung Lin
State retention for power gated design with non-uniform multi-bit retention latches. 607-614 - Zhanwei Zhong, Zipeng Li, Krishnendu Chakrabarty
Adaptive error recovery in MEDA biochips based on droplet-aliquot operations and predictive analysis. 615-622 - Mohamed Ibrahim, Aditya Sridhar, Krishnendu Chakrabarty
Sortex: Efficient timing-driven synthesis of reconfigurable flow-based biochips for scalable single-cell screening. 623-630 - Amar Shrestha, Khadeer Ahmed, Yanzhi Wang, David P. Widemann, Adam T. Moody, Brian C. Van Essen, Qinru Qiu:
A spike-based long short-term memory on a neurosynaptic processor. 631-637 - Meng Yang, John P. Hayes, Deliang Fan, Weikang Qian:
Design of accurate stochastic number generators with noisy emerging devices for stochastic computing. 638-644 - Tengtao Li, Sachin S. Sapatnekar
Stress-aware performance evaluation of 3D-stacked wide I/O DRAMs. 645-650 - Jiangwei Zhang, Donald Kline Jr.
Dynamic partitioning to mitigate stuck-at faults in emerging memories. 651-658 - Sandeep Chatterjee, Valeriy Sukharev, Farid N. Najm:
Fast physics-based electromigration assessment by efficient solution of linear time-invariant (LTI) systems. 659-666 - Changho Han
Optimal multi-row detailed placement for yield and model-hardware correlation improvements in sub-10nm VLSI. 667-674 - Samit Chaudhuri, Asmus Hetzel:
SAT-based compilation to a non-vonNeumann processor. 675-682 - Yeseong Kim, Pietro Mercati
P4: Phase-based power/performance prediction of heterogeneous systems via neural networks. 683-690 - Young-kyu Choi
HLScope+, : Fast and accurate performance estimation for FPGA HLS. 691-698 - Dajung Lee, Alric Althoff, Dustin Richmond
A streaming clustering approach using a heterogeneous system for big data analysis. 699-706 - Wei Hu
Why you should care about don't cares: Exploiting internal don't care conditions for hardware Trojans. 707-713 - Nicole Fern, Kwang-Ting Cheng
Mining mutation testing simulation traces for security and testbench debugging. 714-721 - Kiruba Sankaran Subramani, Angelos Antonopoulos, Ahmed Attia Abotabl, Aria Nosratinia, Yiorgos Makris
ACE: Adaptive channel estimation for detecting analog/RF trojans in WLAN transceivers. 722-727 - Dylan C. Stow, Yuan Xie, Taniya Siddiqua, Gabriel H. Loh:
Cost-effective design of scalable high-performance systems using active and passive interposers. 728-735 - Quan Deng, Youtao Zhang, Minxuan Zhang, Jun Yang:
Towards warp-scheduler friendly STT-RAM/SRAM hybrid GPGPU register file design. 736-742 - Monodeep Kar, Tushar Krishna:
A case for low frequency single cycle multi hop NoCs for energy efficiency and high performance. 743-750 - Jiachen Mao, Zhongda Yang, Wei Wen, Chunpeng Wu, Linghao Song
MeDNN: A distributed mobile system with enhanced partition and deployment for large-scale DNNs. 751-756 - Tsung-Wei Huang, Chun-Xun Lin, Martin D. F. Wong
DtCraft: A distributed execution engine for compute-intensive applications. 757-765 - Lei Zhao, Youtao Zhang, Jun Yang:
AEP: An error-bearing neural network accelerator for energy efficiency and model protection. 765-771 - Mohamed Baker Alawieh
Efficient programming of reconfigurable radio frequency (RF) systems. 772-779 - Shaofeng Guo, Runsheng Wang, Zhuoqing Yu, Peng Hao, Pengpeng Ren, Yangyuan Wang, Siyu Liao, Chunyi Huang, Tianlei Guo, Alvin Chen, Jushan Xie, Ru Huang:
Towards reliability-aware circuit design in nanoscale FinFET technology: - New-generation aging model and circuit reliability simulator. 780-785 - Hongge Chen, Duane S. Boning:
Online and incremental machine learning approaches for IC yield improvement. 786-793 - Xunzhao Yin, Zoltán Toroczkai
An analog SAT solver based on a deterministic dynamical system: (Invited paper). 794-799 - Abhinav Parihar
Connecting spectral techniques for graph coloring and eigen properties of coupled dynamics: A pathway for solving combinatorial optimizations (Invited paper). 800-804 - Kyungwook Chang, Abhishek Koneru, Krishnendu Chakrabarty
Design automation and testing of monolithic 3D ICs: Opportunities, challenges, and solutions: (Invited paper). 805-810 - Shengcheng Wang, Zeyu Sun, Yuan Cheng, Sheldon X.-D. Tan, Mehdi Baradaran Tahoori:
Leveraging recovery effect to reduce electromigration degradation in power/ground TSV. 811-818 - Xiaofan Zhang, Anand Ramachandran, Chuanhao Zhuge, Di He, Wei Zuo, Zuofu Cheng, Kyle Rupnow, Deming Chen:
Machine learning on FPGAs to face the IoT revolution. 819-826 - Kang Yao, Yaoyao Ye, Sudeep Pasricha, Jiang Xu:
Thermal-sensitive design and power optimization for a 3D torus-based optical NoC. 827-834 - Zhuwei Qin, Zirui Xu, Qide Dong, Yiran Chen, Xiang Chen:
VoCaM: Visualization oriented convolutional neural network acceleration on mobile system: Invited paper. 835-840 - Xiaodao Chen, Dongmei Zhang, Yuewei Wang, Lizhe Wang, Albert Y. Zomaya
Offshore oil spill monitoring and detection: Improving risk management for offshore petroleum cyber-physical systems: (Invited paper). 841-846 - Hongjia Li, Tianshu Wei, Ao Ren, Qi Zhu
Deep reinforcement learning: Framework, applications, and embedded implementations: Invited paper. 847-854 - Myung-Chul Kim, Shih-Hsu Huang, Rung-Bin Lin, Shigetoshi Nakatake:
Overview of the 2017 CAD contest at ICCAD: Invited paper. 855-856 - Ching-Yi Huang, Chih-Jen Hsu, Chi-An Wu, Kei-Yong Khoo:
ICCAD-2017 CAD contest in resource-aware patch generation. 857-862 - Kai-Shun Hu, Ming-Jen Yang, Yu-Hui Huang, Bing-Yi Wong, Cindy Chin-Fang Shen:
ICCAD-2017 CAD contest in net open location finder with obstacles: Invited paper. 863-866 - Nima Karimpour Darav, Ismail S. Bustany, Andrew A. Kennings, Ravi Mamidi:
ICCAD-2017 CAD contest in multi-deck standard cell legalization and benchmarks. 867-871 - Jinwook Jung, Pei-Yu Lee, Yan-Shiun Wu, Nima Karimpour Darav, Iris Hui-Ru Jiang, Victor N. Kravets, Laleh Behjat
DATC RDF: Robust design flow database: Invited paper. 872-873 - Yuichi Nakamura, Hideyuki Shimonishi, Yuki Kobayashi, Kozo Satoda
Novel heterogeneous computing platforms and 5G communications for IoT applications. 874-879 - Xiaowei Xu
Edge segmentation: Empowering mobile telemedicine with compressed cellular neural networks. 880-887 - Jinyang Li, Qingwei Guo, Fang Su, Zhe Yuan, Jinshan Yue, Jingtong Hu, Huazhong Yang, Yongpan Liu:
CNN-based pattern recognition on nonvolatile IoT platform for smart ultraviolet monitoring: (Invited paper). 888-893 - Xiaofan Zhang, Anand Ramachandran, Chuanhao Zhuge, Di He, Wei Zuo, Zuofu Cheng, Kyle Rupnow, Deming Chen:
Machine learning on FPGAs to face the IoT revolution. 894-901 - Mingze Gao, Gang Qu:
Energy efficient runtime approximate computing on data flow graphs. 902-907 - Elliott Delaye, Ashish Sirasao, Chaithanya Dudha, Sabya Das:
Deep learning challenges and solutions with Xilinx FPGAs. 908-913 - Shih-Chun Chen, Yao-Wen Chang:
FPGA placement and routing. 914-921 - Wuxi Li, Meng Li, Jiajun Wang, David Z. Pan:
UTPlaceF 3.0: A parallelization framework for modern FPGA global placement: (Invited paper). 922-928 - Chak-Wa Pui, Gengjie Chen, Yuzhe Ma, Evangeline F. Y. Young, Bei Yu:
Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper). 929-936 - Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang:
A hybrid approach to cache management in heterogeneous CPU-FPGA platforms. 937-944 - Xun Jiao, Mulong Luo, Jeng-Hau Lin, Rajesh K. Gupta:
An assessment of vulnerability of hardware neural networks to dynamic voltage and temperature variations. 945-950 - Yu Jiang, Mingzhe Wang, Han Liu, Mohammad Hosseini, Jiaguang Sun:
Dependable integrated clinical system architecture with runtime verification. 951-956 - Andrew Y.-Z. Ou, Maryam Rahmaniheris, Yu Jiang, Po-Liang Wu, Lui Sha:
Toward safe interoperations in network connected medical cyber-physical systems using open-loop safe protocols. 957-963 - Chunhui Guo
Model and integrate medical resource availability into verifiably correct executable medical guidelines. 964-969 - Alessandra Nardi, Antonino Armato:
Functional safety methodologies for automotive applications. 970-975 - Handi Yu, Changhao Yan, Xuan Zeng, Xin Li:
Impact of circuit-level non-idealities on vision-based autonomous driving systems. 976-983 - Bowen Zheng, Muhammed O. Sayin
Timing and security analysis of VANET-based intelligent transportation systems: (Invited paper). 984-991 - Vinay Vashishtha, Manoj Vangala, Lawrence T. Clark:
ASAP7 predictive design kit development and cell design technology co-optimization: Invited paper. 992-998 - Xiaoqing Xu, Nishi Shah, Andrew Evans, Saurabh Sinha, Brian Cline, Greg Yeric:
Standard cell library design and optimization methodology for ASAP7 PDK: (Invited paper). 999-1004 - Kyungwook Chang, Bon Woong Ku, Saurabh Sinha, Sung Kyu Lim
Full-chip monolithic 3D IC design and power performance analysis with ASAP7 library: (Invited Paper). 1005-1010 - Jonathan Bachrach, Albert Magyar, Daniel Palmer Dabbelt, Patrick Li, Richard Lin, Krste Asanovic:
Cyclist: Accelerating hardware development. 1011-1018 - Keerthikumara Devarajegowda, Johannes Schreiner, Rainer Findenig, Wolfgang Ecker:
Python based framework for HDSLs with an underlying formal semantics: (Invited paper). 1019-1025 - Oliver Reiche, M. Akif Ozkan, Richard Membarth, Jürgen Teich, Frank Hannig
Generating FPGA-based image processing accelerators with Hipacc: (Invited paper). 1026-1033 - Sandip Ray:
Transportation security in the era of autonomous vehicles: Challenges and practice. 1034-1038 - Sujit Rokka Chhetri, Nafiul Rashid, Sina Faezi, Mohammad Abdullah Al Faruque
Security trends and advances in manufacturing systems in the era of industry 4.0. 1039-1046 - Lei Zhao, Youtao Zhang, Jun Yang:
AEP: An error-bearing neural network accelerator for energy efficiency and model protection. 1047-1053 - Yujie Wang, Tri Cao, Jiang Hu, Jeyavijayan Rajendran:
Front-end-of-line attacks in split manufacturing. 1-8
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