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ISSCC 2013: San Francisco, CA, USA
- 2013 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2013, San Francisco, CA, USA, February 17-21, 2013. IEEE 2013, ISBN 978-1-4673-4515-6
- Laura Chizuko Fujino:
Welcome! 1 - Laura Chizuko Fujino:
Reflections. 4 - Anantha P. Chandrakasan, Bram Nauta:
Session 1 overview: Plenary session. 6-7 - Lisa T. Su:
"Architecting the future through heterogeneous computing". 8-11 - Yoshiyuki Miyabe:
"Smart life solutions" from home to city. 12-17 - Martin van den Brink:
Continuing to shrink: Next-generation lithography - Progress and prospects. 20-25 - Carver Mead:
The evolution of technology. 26 - Ken Chang, Hisakatsu Yamaguchi:
Session 2 overview: Ultra-high-speed transceivers and equalizers. 26-27 - Samir Parikh, Tony Kao, Yasuo Hidaka, Jian Jiang, Asako Toda, Scott McLeod, William W. Walker, Yoichi Koyanagi, Toshiyuki Shibuya, Jun Yamada:
A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS. 28-29 - Yue Lu, Elad Alon:
A 66Gb/s 46mW 3-tap decision-feedback equalizer in 65nm CMOS. 30-31 - Bharath Raghavan, Delong Cui, Ullas Singh, Hassan Maarefi, Dave Pi, Anand Vasani, Zhi Chao Huang, Afshin Momtaz, Jun Cao:
A sub-2W 39.8-to-44.6Gb/s transmitter and receiver chipset with SFI-5.2 interface in 40nm CMOS. 32-33 - Bo Zhang, Ali Nazemi, Adesh Garg, Namik Kocaman, Mahmoud Reza Ahmadi, Mehdi Khanpour, Heng Zhang, Jun Cao, Afshin Momtaz:
A 195mW / 55mW dual-path receiver AFE for multistandard 8.5-to-11.5 Gb/s serial links in 40nm CMOS. 34-35 - Yoshiyasu Doi, Takayuki Shibasaki, Takumi Danjo, Win Chaivipas, Takushi Hashida, Hiroki Miyaoka, Masanori Hoshino, Yoichi Koyanagi, Takuji Yamamoto, Sanroku Tsukamoto, Hirotaka Tamura:
32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS. 36-37 - Amr Amin Hafez, Ming-Shuan Chen, Chih-Kong Ken Yang:
A 32-to-48Gb/s serializing transmitter using multiphase sampling in 65nm CMOS. 38-39 - Yuuki Ogata, Yasuo Hidaka, Yoichi Koyanagi, Sadanori Akiya, Yuji Terao, Kosuke Suzuki, Keisuke Kashiwa, Masanobu Suzuki, Hirotaka Tamura:
32Gb/s 28nm CMOS time-interleaved transmitter compatible with NRZ receiver with DFE. 40-41 - Kwangmo Jung, Amir Amirkhany, Kambiz Kaviani:
A 0.94mW/Gb/s 22Gb/s 2-tap partial-response DFE receiver in 40nm LP CMOS. 42-43 - Se-Hyun Yang, Eric Fluhr:
Session 3 overview: Processors. 44-45 - James D. Warnock, Yuen H. Chan, Hubert Harrer, David L. Rude, Ruchir Puri, Sean M. Carey, Gerard Salem, Guenter Mayer, Yiu-Hing Chan, Mark D. Mayo, Adam Jatkowski, Gerald Strevig, Leon J. Sigal, Ayan Datta, Anne Gattiker, Aditya Bansal, Doug Malone, Thomas Strach, Huajun Wen, Pak-kin Mak, Chung-Lung Kevin Shum, Donald W. Plass, Charles F. Webb:
5.5GHz system z microprocessor and multi-chip module. 46-47 - Jason Hart, Steve Butler, Hoyeol Cho, Yuefei Ge, Gregory Gruber, Dawei Huang, Changku Hwang, Daisy Jian, Timothy Johnson, Georgios K. Konstadinidis, Lance Kwong, Robert P. Masleid, Umesh Nawathe, Aparna Ramachandran, Yongning Sheng, Jinuk Luke Shin, Sebastian Turullols, Zuxu Qin, King C. Yen:
3.6GHz 16-core SPARC SoC processor in 28nm. 48-49 - Jen-Wei Lee, Szu-Chi Chung
, Hsie-Chia Chang, Chen-Yi Lee:
Processor with side-channel attack resistance. 50-51 - Teja Singh, Joshua Bell, Shane Southard:
Jaguar: A next-generation low-power x86-64 core. 52-53 - Weiwu Hu, Yifu Zhang, Liang Yang, Bao-Xia Fan, Yunji Chen
Godson-3B1500: A 32nm 1.35GHz 40W 172.8GFLOPS 8-core processor. 54-55 - Peng Ou, Jiajie Zhang, Heng Quan, Yi Li, Maofei He, Zheng Yu, Xueqiu Yu, Shile Cui, Jie Feng, Shikai Zhu, Jie Lin, Ming-e Jing, Xiaoyang Zeng, Zhiyi Yu:
A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array. 56-57 - Venkatram Krishnaswamy, Dawei Huang, Sebastian Turullols, Jinuk Luke Shin:
Bandwidth and power management of glueless 8-socket SPARC T5 system. 58-59 - Ryuji Kan, Tomohiro Tanaka, Go Sugizaki, Ryuichi Nishiyama, Sota Sakabayashi, Yoichi Koyanagi, Ryuji Iwatsuki, Kazumi Hayasaka, Taiki Uemura, Gaku Ito, Yoshitomo Ozeki, Hiroyuki Adachi, Kazuhiro Furuya, Tsuyoshi Motokurumada:
A 10th generation 16-core SPARC64 processor for mission-critical UNIX server. 60-61 - Jae-Youl Lee, Saska Lindfors:
Session 4 overview: Harvesting & wireless power. 62-63 - Jun-Han Choi, Sung-Ku Yeo, Chang-Byong Park, Seho Park, Jeong Seok Lee, Gyu-Hyeong Cho:
A resonant regulating rectifier (3R) operating at 6.78 MHz for a 6W wireless charger with 86% efficiency. 64-65 - Yan Lu
A 13.56MHz fully integrated 1X/2X active rectifier with compensated bias current for inductively powered devices. 66-67 - Kin Wai Roy Chew, Zhuochao Sun
A 400nW single-inductor dual-input-tri-output DC-DC buck-boost converter with maximum power point tracking for indoor photovoltaic energy harvesting. 68-69 - Wen-Chuen Liu, Yi-Hsiang Wang, Tai-Haur Kuo:
An adaptive load-line tuning IC for photovoltaic module integrated mobile device with 470µs transient time, over 99% steady-state accuracy and 94% power conversion efficiency. 70-71 - Tsung-Heng Tsai
A 3.4mW photovoltaic energy-harvesting charger with integrated maximum power point tracking and battery management. 72-73 - Stefano Stanzione, Chris van Liempd, Rob van Schaijk, Yasuyuki Naito, Refet Firat Yazicioglu, Chris Van Hoof
A self-biased 5-to-60V input voltage and 25-to-1600µW integrated DC-DC buck converter with fully analog MPPT algorithm reaching up to 88% end-to-end efficiency. 74-75 - Chris van Liempd, Stefano Stanzione, Younis Allasasmeh, Chris Van Hoof:
A 1µW-to-1mW energy-aware interface IC for piezoelectric harvesting with 40nA quiescent current and zero-bias active rectifiers. 76-77 - Dongwon Kwon, Gabriel A. Rincón-Mora:
A single-inductor 0.35µm CMOS energy-investing piezoelectric harvester. 78-79 - Mike Keaveney, Joe Golat:
Session 5 overview: RF techniques. 80-81 - Ivan Fabiano, Marco Sosio, Antonio Liscidini
SAW-less analog front-end receivers for TDD and FDD. 82-83 - Amir Ghaffari, Eric A. M. Klumperink, Frank E. van Vliet, Bram Nauta
Simultaneous spatial and frequency-domain filtering at the antenna inputs achieving up to +10dBm out-of-band/beam P1dB. 84-85 - Mohyee Mikhemar, David Murphy, Ahmad Mirzaei, Hooman Darabi:
A phase-noise and spur filtering technique using reciprocal-mixing cancellation. 86-87 - Maryam Fathi, David K. Su, Bruce A. Wooley:
A 30.3dBm 1.9GHz-bandwidth 2×4-array stacked 5.3GHz CMOS power amplifier. 88-89 - Kohei Onizuka, Shigehito Saigusa, Shoji Otaka:
A 1.8GHz linear CMOS power amplifier with supply-path switching scheme for WCDMA/LTE applications. 90-91 - Sang-Sung Lee, Jaeheon Lee, In-Young Lee, Sang-Gug Lee, Jinho Ko:
A new TX leakage-suppression technique for an RFID receiver using a dead-zone amplifier. 92-93 - Frederic Roger:
A 200mW 100MHz-to-4GHz 11th-order complex analog memory polynomial predistorter for wireless infrastructure RF amplifiers. 94-95 - David Ruffieux, Yogesh K. Ramadass:
Session 6 overview: Emerging medical and sensor technologies technology directions subcommittee. 96-97 - Kiseok Song, Unsoo Ha, Jaehyuk Lee, Kyeongryeol Bong, Hoi-Jun Yoo:
An 87mA·min iontophoresis controller IC with dual-mode impedance sensor for patch-type transdermal drug delivery system. 98-99 - Muhammad Awais Bin Altaf
A 1.83µJ/classification nonlinear support-vector-machine-based patient-specific seizure classification SoC. 100-101 - Chih-Wei Chang, Po-Tsang Huang, Lei-Chun Chou, Shang-Lin Wu, Shih-Wei Lee, Ching-Te Chuang, Kuan-Neng Chen
Through-silicon-via-based double-side integrated microsystem for neural sensing applications. 102-103 - Hiroshi Fuketa, Kazuaki Yoshioka, Yasuhiro Shinozuka, Koichi Ishida, Tomoyuki Yokota, Naoji Matsuhisa, Yusuke Inoue, Masaki Sekino, Tsuyoshi Sekitani, Makoto Takamiya, Takao Someya, Takayasu Sakurai:
1µm-thickness 64-channel surface electromyogram measurement sheet with 2V organic transistors for prosthetic hand control. 104-105 - Sahel Abdinia, Mohamed Benwadih
A 4b ADC manufactured in a fully-printed organic complementary technology including resistors. 106-107 - Daniele Raiteri, Pieter van Lieshout, Arthur H. M. van Roermund, Eugenio Cantatore:
An organic VCO-based ADC for quasi-static signals achieving 1LSB INL at 6b resolution. 108-109 - Yuki Maruyama, Jordana Blacksberg, Edoardo Charbon:
A 1024×8 700ps time-gated SPAD line sensor for laser raman spectroscopy and LIBS in space and rover-based planetary exploration. 110-111 - Max M. Shulaker, Jelle Van Rethy, Gage Hills, Hong-Yu Chen, Georges G. E. Gielen, H.-S. Philip Wong, Subhasish Mitra
Experimental demonstration of a fully digital capacitive sensor interface built entirely using carbon-nanotube FETs. 112-113 - Ichiro Fujimori, Masafumi Nogawa:
Session 7 overview: Optical transceivers and silicon photonics. 114-115 - Georgios Kalogerakis, Tim Moran, Thelinh Nguyen, Gilles Denoyer:
A quad 25Gb/s 270mW TIA in 0.13µm BiCMOS with <0.15dB crosstalk penalty. 116-117 - Takashi Takemoto, Hiroki Yamashita, Toru Yazaki, Norio Chujo, Yong Lee, Yasunobu Matsuoka:
A 4× 25-to-28Gb/s 4.9mW/Gb/s -9.7dBm high-sensitivity optical receiver based on 65nm CMOS for board-to-board interconnects. 118-119 - Jhih-Yu Jiang, Ping-Chuan Chiang, Hao-Wei Hung, Chen-Lun Lin, Ty Yoon, Jri Lee:
100Gb/s ethernet chipsets in 65nm CMOS technology. 120-121 - Clifford Ting, Joshua Liang
A blind baud-rate ADC-based CDR. 122-123 - Cheng Li, Rui Bai, Ayman Shafik, Ehsan Zhian Tabasy, Geng Tang, Chao Ma, Chin-Hui Chen, Zhen Peng, Marco Fiorentino
A ring-resonator-based silicon photonics transceiver with bias-based wavelength stabilization and adaptive-power-sensitivity receiver. 124-125 - Benjamin Moss, Chen Sun, Michael Georgas, Jeffrey Shainline, Jason Orcutt, Jonathan C. Leu, Mark T. Wade, Yu-Hsin Chen, Kareem Nammari, Xiaoxi Wang, Hanqing Li, Rajeev J. Ram, Milos A. Popovic
A 1.23pJ/b 2.5Gb/s monolithically integrated optical carrier-injection ring modulator and all-digital driver circuit in commercial 45nm SOI. 126-127 - Xiaotie Wu, Bipin Dama, Prakash Gothoskar, Peter Metz, Kal Shastri, Sanjay Sunder, Jan Van der Spiegel, Yifan Wang, Mark Webster, Will Wilson:
A 20Gb/s NRZ/PAM-4 1V transmitter in 40nm CMOS driving a Si-photonic modulator in 0.13µm CMOS. 128-129 - Jonathan E. Proesel, Alexander V. Rylyakov, Clint Schow:
Optical receivers using DFE-IIR equalization. 130-131 - Yi Zhao, Leonardo Vera, John R. Long, David L. Harame:
A 10Gb/s 6Vpp differential modulator driver in 0.18µm SiGe-BiCMOS. 132-133 - Ullrich R. Pfeiffer, Gabriel M. Rebeiz:
Session 8 overview: Millimeter-wave techniques. 134-135 - Zheng Wang, Pei-Yuan Chiang, Peyman Nazari, Chun-Cheng Wang, Zhiming Chen, Payam Heydari:
A 210GHz fully integrated differential transceiver with fundamental-frequency VCO in 32nm SOI CMOS. 136-137 - Ruonan Han, Ehsan Afshari:
A 260GHz broadband source with 1.1mW continuous-wave radiated power and EIRP of 15.7dBm in 65nm CMOS. 138-139 - Omeed Momeni:
A 260GHz amplifier with 9.2dB gain and -3.9dBm saturated power in 65nm CMOS. 140-141 - Wei Tai, L. Richard Carley, David S. Ricketts:
A 0.7W fully integrated 42GHz power amplifier with 10% PAE in 0.13µm SiGe BiCMOS. 142-143 - Francis Caster, Leland Gilreath, Shiji Pan, Zheng Wang, Filippo Capolino
A 93-to-113GHz BiCMOS 9-element imaging array receiver utilizing spatial-overlapping pixels with wideband phase and amplitude control. 144-145 - Pang-Ning Chen, Pen-Jui Peng
A 94GHz 3D-image radar engine with 4TX/4RX beamforming scan technique in 65nm CMOS. 146-147 - Yaoming Sun, Miroslav Marinkovic, Gunter Fischer, Wolfgang Winkler, Wojciech Debski, Stefan Beer, Thomas Zwick
A low-cost miniature 120GHz SiP FMCW/CW radar sensor with software linearization. 148-149 - Qiyang Wu, Tony Quach, Aji Mattamana, Salma Elabd, Steven R. Dooley, Jamin J. McCue, Pompei L. Orlando, Gregory L. Creech, Waleed Khalil:
A 10mW 37.8GHz current-redistribution BiCMOS VCO with an average FOMT of -193.5dBc/Hz. 150-151 - Michael Polley, Yongha Park:
Session 9 overview: Mobile application processors and media accelerators. 152-153 - Youngmin Shin, Ken Shin, Prashant Kenkare, Rajesh Kashyap, Hoi-Jin Lee, Dongjoo Seo, Brian Millar, Yohan Kwon, Ravi Iyengar, Min-Su Kim, Ahsan Chowdhury, Sung-il Bae, Inpyo Hong, Wookyeong Jeong, Aaron Lindner, Ukrae Cho, Keith Hawkins, Jae-Cheol Son, Seung Ho Hwang:
28nm high- metal-gate heterogeneous quad-core CPUs for high-performance and energy-efficient mobile application processor. 154-155 - Masaki Fujigaya, Noriaki Sakamoto, Takao Koike, Takahiro Irita, Kohei Wakahara, Tsugio Matsuyama, Keiji Hasegawa, Toshiharu Saito, Akira Fukuda, Kaname Teranishi, Kazuki Fukuoka, Noriaki Maeda, Koji Nii, Takeshi Kataoka, Toshihiro Hattori:
A 28nm High-κ metal-gate single-chip communications processor with 1.5GHz dual-core application processor and LTE/HSPA+-capable baseband processor. 156-157 - Tay-Jyi Lin, Cheng-An Chien, Pei-Yao Chang, Ching-Wen Chen, Po-Hao Wang, Ting-Yu Shyu, Chien-Yung Chou, Shien-Chun Luo, Jiun-In Guo, Tien-Fu Chen, Gene C. H. Chuang, Yuan-Hua Chu, Liang-Chia Cheng, Hong-Men Su, Chewnpu Jou, Meikei Ieong, Cheng-Wen Wu
A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. 158-159 - Yongha Park, Chang-Hyo Yu, Kilwhan Lee, Hyunsuk Kim, Youngeun Park, Chun-Ho Kim, Yunseok Choi, Jinhong Oh, Changhoon Oh, Gurnrack Moon, Sangduk Kim, Horang Jang, Jin-Aeon Lee, Chinhyun Kim, Sungho Park:
72.5GFLOPS 240Mpixel/s 1080p 60fps multi-format video codec application processor enabled with GPGPU for fused multimedia application. 160-161 - Chao-Tsung Huang, Mehul Tikekar, Chiraag Juvekar, Vivienne Sze, Anantha P. Chandrakasan:
A 249Mpixel/s HEVC video-decoder chip for Quad Full HD applications. 162-163 - Rahul Rithe, Priyanka Raina, Nathan Ickes, Srikanth V. Tenneti, Anantha P. Chandrakasan:
Reconfigurable processor for energy-scalable computational photography. 164-165 - Dongsuk Jeon, Yejoong Kim
A 470mV 2.7mW feature extraction-accelerator for micro-autonomous vehicle navigation in 28nm CMOS. 166-167 - Junyoung Park, Injoon Hong, Gyeonghoon Kim, Youchang Kim
A 646GOPS/W multi-classifier many-core processor with cortex-like architecture for super-resolution recognition. 168-169 - Jafar Savoj, Chris Mangelsdorf:
Session 10 overview: Analog techniques. 170-171 - Milad Darvishi, Ronan A. R. van der Zee
A 0.1-to-1.2GHz tunable 6th-order N-path channel-select filter with 0.6dB passband ripple and +7dBm blocker tolerance. 172-173 - Massoud Tohidian
A 2mW 800MS/s 7th-order discrete-time IIR filter with 400kHz-to-30MHz BW and 100dB stop-band rejection in 65nm CMOS. 174-175 - Qinwen Fan, Johan H. Huijsing, Kofi A. A. Makinwa:
A multi-path chopper-stabilized capacitively coupled operational amplifier with 20V-input-common-mode range and 3µV offset. 176-177 - Ippei Akita
A 0.06mm2 14nV/√Hz chopper instrumentation amplifier with automatic differential-pair matching. 178-179 - Marco Berkhout, Lutsen Dooper, Benno Krabbenborg, John Somberg:
A 4Ω 2.3W class-D audio amplifier with embedded DC-DC boost converter, current-sensing ADC and DSP for adaptive speaker protection. 180-181 - Jianlong Chen, Sasi Kumar Arunachalam, Todd Brooks, Iuri Mehr, Felix Cheung, Hariprasath Venkatram:
A 62mW stereo class-G headphone driver with 108dB dynamic range and 600µA/channel quiescent current. 182-183 - Arun Paidimarri, Danielle Griffith
A 120nW 18.5kHz RC oscillator with comparator offset cancellation for ±0.25% temperature stability. 184-185 - Ying Cao, Paul Leroux
A 63, 000 Q-factor relaxation oscillator with switched-capacitor integrated error feedback. 186-187 - Dong-Woo Jee, Dennis Sylvester, David T. Blaauw, Jae-Yoon Sim:
A 0.45V 423nW 3.2MHz multiplying DLL with leakage-based oscillator for ultra-low-power sensor platforms. 188-189 - Fu-Lung Hsueh, Shinichiro Mutoh:
Session 11 overview: Emerging memory and wireless technology. 190-191 - Masood Qazi, Ajith Amerasekera, Anantha P. Chandrakasan:
A 3.4pJ FeRAM-enabled D flip-flop in 0.13µm CMOS for nonvolatile processing in digital systems. 192-193 - Masanori Natsui
Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating. 194-195 - David Ruffieux, Nicola Scolari, Frédéric Giroud, Thanh-Chau Le, Silvio Dalla Piazza, Felix Staub, Kai Zoschke, Charles Alix Manier, Hermann Oppermann
A versatile timing microsystem based on wafer-level packaged XTAL/BAW resonators with sub-µW RTC mode and programmable HF clocks. 196-197 - Francesco Massel
Microwave amplification with nanomechanical resonators. 198-199 - Wataru Mizuhara, Tsunaaki Shidei, Atsutake Kosuge, Tsutomu Takeya, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda:
A 0.15mm-thick non-contact connector for MIPI using vertical directional coupler. 200-201 - Hyunwoo Cho, Unsoo Ha, Taehwan Roh
1.2Gb/s 3.9pJ/b mono-phase pulse-modulation inductive-coupling transceiver for mm-range board-to-board communication. 202-203 - Haruki Fukuda, Takahide Terada, Tadahiro Kuroda:
Retrodirective transponder array with universal on-sheet reference for wireless mobile sensor networks without battery or oscillator. 204-205 - Nachiket V. Desai, Jerald Yoo
A scalable 2.9mW 1Mb/s eTextiles body area network transceiver with remotely powered sensors and bi-directional data communication. 206-207 - Jin-Man Han, Daniele Vimercati:
Session 12 overview: Non-volatile memory solutions. 208-209 - Tz-Yi Liu, Tian Hong Yan, Roy Scheuerlein, Yingchang Chen, Jeffrey KoonYee Lee, Gopinath Balakrishnan, Gordon Yee, Henry Zhang, Alex Yap, Jingwen Ouyang, Takahiko Sasaki, Sravanti Addepalli, Ali Al-Shamma, Chin-Yu Chen, Mayank Gupta, Greg Hilton, Saurabh Joshi, Achal Kathuria, Vincent Lai, Deep Masiwal, Masahide Matsumoto, Anurag Nigam, Anil Pai, Jayesh Pakhale, Chang Hua Siau, Xiaoxia Wu, Ronald Yin, Liping Peng, Jang Yong Kang, Sharon Huynh, Huijuan Wang, Nicolas Nagel, Yoichiro Tanaka, Masaaki Higashitani, Tim Minvielle, Chandu Gorla, Takayuki Tsukamoto, Takeshi Yamaguchi, Mutsumi Okajima, Takayuki Okamura, Satoru Takase, Takahiko Hara, Hirofumi Inoue, Luca Fasoli, Mehrdad Mofidi, Ritu Shrivastava, Khandker Quader:
A 130.7mm2 2-layer 32Gb ReRAM memory device in 24nm technology. 210-211 - Takashi Kono, Takashi Ito, Tamaki Tsuruda, Takayuki Nishiyama, Tsutomu Nagasawa, Tomoya Ogawa, Yoshiyuki Kawashima, Hideto Hidaka, Tadaaki Yamauchi:
40nm embedded SG-MONOS flash macros for automotive with 160MHz random access for code and endurance over 10M cycles for data. 212-213 - Noriyuki Miura, Mitsuko Saito, Masao Taguchi, Tadahiro Kuroda:
A 6nW inductive-coupling wake-up transceiver for reducing standby power of non-contact memory card by 500×. 214-215 - Mihail Jefremow, Thomas Kern, Wolf Allers, Christian Peters, Jan Otterstedt, Othmane Bahlous, Karl Hofmann, Robert Allinger, Stephan Kassenetter, Doris Schmitt-Landsiedel:
Time-differential sense amplifier for sub-80mV bitline voltage embedded STT-MRAM in 40nm CMOS. 216-217 - Giovanni Naso, L. Botticchio, M. Castelli, C. Cerafogli, M. Cichocki, P. Conenna, Andrea D'Alessandro, Luca De Santis, Domenico Di Cicco, W. Di Francesco, M. L. Gallese, Girolamo Gallo, Michele Incarnati, C. Lattaro, Agostino Macerola, G. G. Marotta, Violante Moschiano, D. Orlandi, F. Paolini, S. Perugini, Luigi Pilolli, P. Pistilli, G. Rizzo, F. Rori, Massimo Rossini, Giovanni Santin, Emanuele Sirizotti, A. Smaniotto, U. Siciliani, Marco Tiburzi, R. Meyer, A. Goda, B. Filipiak, Tommaso Vali, Mark Helm, Ramin Ghodsi:
A 128Gb 3b/cell NAND flash design using 20nm planar-cell technology. 218-219 - Akifumi Kawahara, Ken Kawai, Yuuichirou Ikeda, Yoshikazu Katoh, Ryotaro Azuma, Yuhei Yoshimoto, Kouhei Tanabe, Zhiqiang Wei, Takeki Ninomiya, Koji Katayama, Ryutaro Yasuhara, Shunsaku Muraoka, Atsushi Himeno, Naoki Yoshikawa, Hideaki Murase
Filament scaling forming technique and level-verify-write scheme with endurance over 107 cycles in ReRAM. 220-221 - Kin-Chu Ho, Po-Chao Fang, Hsiang-Pang Li, Cheng-Yuan Michael Wang, Hsie-Chia Chang:
A 45nm 6b/cell charge-trapping flash memory using LDPC-based ECC and drift-immune soft-sensing engine. 222-223 - Hung-Chang Yu, Kai-Chun Lin, Ku-Feng Lin, Chin-Yi Huang, Yu-Der Chih, Tong-Chern Ong, Tsung-Yung Jonathan Chang, Sreedhar Natarajan, Luan C. Tran:
Cycling endurance optimization scheme for 1Mb STT-MRAM in 40nm technology. 224-225 - Shuhei Tanakamaru, Masafumi Doi, Ken Takeuchi:
Unified solid-state-storage architecture with NAND flash memory and ReRAM that tolerates 32× higher BER for big-data applications. 226-227 - Brian A. Floyd, Kenichi Okada:
Session 13 overview: High-performance wireless. 228-229 - Takayuki Tsukizawa, Naganori Shirakata, Tadashi Morita, Koichiro Tanaka, Junji Sato, Yohei Morishita, Masaki Kanemaru, Ryo Kitamura, Takahiro Shima, Toshifumi Nakatani, Kenji Miyanaga, Tomoya Urushihara, Hiroyuki Yoshikawa, Takenori Sakamoto, Hiroyuki Motozuka
A fully integrated 60GHz CMOS transceiver chipset based on WiGig/IEEE802.11ad with built-in self calibration for mobile applications. 230-231 - Jiashu Chen, Lu Ye, Diane Titz, Fred Gianesello, Romain Pilard, Andreia Cathelin, Fabien Ferrero, Cyril Luxey, Ali M. Niknejad:
A digitally modulated mm-Wave cartesian beamforming transmitter with quadrature spatial combining. 232-233 - Lingkai Kong, Dongjin Seo, Elad Alon:
A 50mW-TX 65mW-RX 60GHz 4-element phased-array transceiver with integrated antennas in 65nm CMOS. 234-235 - Vojkan Vidojkovic, Viki Szortyka, Khaled Khalaf, Giovanni Mangraviti
A low-power radio chipset in 40nm LP CMOS with beamforming for 60GHz high-data-rate wireless communication. 236-237 - Chintan Thakkar, Nathan Narevsky, Christopher D. Hull, Elad Alon:
A mixed-signal 32-coefficient RX-FFE 100-coefficient DFE for an 8Gb/s 60GHz receiver in 65nm LP CMOS. 238-239 - Michele Caruso, Matteo Bassi
A 2-to-16GHz 204mW 3mm-resolution stepped-frequency radar for breast-cancer diagnostic imaging in 65nm CMOS. 240-241 - Chang-Ming Lai, Jen-Ming Wu, Po-Chiun Huang, Ta-Shun Chu:
A scalable direct-sampling broadband radar receiver supporting simultaneous digital multibeam array in 65nm CMOS. 242-243 - Weinan Gao, Bill Huff, Kendal Hess, Didier Coulibaly, Costantino Pala, Jiang Cao, Jaspreet Bhatia, Mikko Waltari, Lior Levin, Cyrille Cathelin, Thierry Nouvet, Nitin Nidhi, Rahul M. Kodkani, Ryuji Maeda, Damian Costa, Jason McFee, Reza Moazzam, Herve Vincent, Philippe Durieux:
A digital single-wire multiswitch (DSWM) channel-stacking IC in 45nm CMOS for satellite outdoor units. 244-245 - Anthony Hill, Atsuki Inoue:
Session 14 overview: Digital PLLs and building blocks. 246-247 - Wei Deng, Ahmed Musa, Teerachot Siriburanon
A 0.022mm2 970µW dual-loop injection-locked PLL with -243dB FOM using synthesizable all-digital PVT calibration circuits. 248-249 - Wooseok Kim, Jaejin Park, Jihyun F. Kim, Taeik Kim, Hojin Park, Deog-Kyoon Jeong:
A 0.032mm2 3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10-to-630MHz DCO tuning range. 250-251 - Nicola Da Dalt, Peter Pridnig, Werner Grollitsch:
An all-digital PLL using random modulation for SSC generation in 65nm CMOS. 252-253 - Tae-Kwang Jang
A 0.026mm2 5.3mW 32-to-2000MHz digital fractional-N phase locked-loop using a phase-interpolating phase-to-digital converter. 254-255 - Tejasvi Anand, Mrunmay Talegaonkar, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu:
A 2.5GHz 2.2mW/25µW on/off-state power 2psrms-long-term-jitter digital clock multiplier with 3-reference-cycles power-on time. 256-257 - Yasuhiro Take, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
3D clock distribution using vertically/horizontally-coupled resonators. 258-259 - Seungwook Paek, Wongyu Shin, Jaeyoung Lee, Hyo-Eun Kim, Jun-Seok Park, Lee-Sup Kim:
All-digital hybrid temperature sensor network for dense thermal monitoring. 260-261 - Seon-Kyoo Lee
A 95fJ/b current-mode transceiver for 10mm on-chip interconnect. 262-263 - Seongjong Kim, Inyong Kwon, David Fick, Myungbo Kim, Yen-Po Chen, Dennis Sylvester:
Razor-lite: A side-channel error-detection register for timing-margin recovery in 45nm SOI CMOS. 264-265 - Michael H. Perrott, Geert Van der Plas
Session 15 overview: Data converter techniques. 266-267 - Yun-Shiang Shu, Jui-Yuan Tsai, Ping Chen, Tien-Yu Lo, Pao-Cheng Chiu:
A 28fJ/conv-step CT ΔΣ modulator with 78dB DR and 18MHz BW in 28nm CMOS using a highly digital multibit quantizer. 268-269 - Pieter Harpe, Eugenio Cantatore, Arthur H. M. van Roermund:
A 2.2/2.7fJ/conversion-step 10/12b 40kS/s SAR ADC with Data-Driven Noise Reduction. 270-271 - Takashi Morie, Takuji Miki, Kazuo Matsukawa, Yoji Bando, Takeshi Okumoto, Koji Obata, Shiro Sakiyama, Shiro Dosho:
A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise. 272-273 - Chao Chen, Zhichao Tan, Michiel A. P. Pertijs:
A 1V 14b self-timed zero-crossing-based incremental ΔΣ ADC. 274-275 - Youngcheol Chae, Kamran Souri, Kofi A. A. Makinwa:
A 6.3µW 20b incremental zoom-ADC with 6ppm INL and 1µV offset. 276-277 - Roddy C. McLachlan, Alan Gillespie, Michael C. W. Coln, Douglas Chisholm, Denise T. Lee:
A 20b clockless DAC with sub-ppm-linearity 7.5nV/vHz-noise and 0.05ppm/°C-stability. 278-279 - Chang-Yuan Liou, Chih-Cheng Hsieh:
A 2.4-to-5.2fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with charge-average switching DAC in 90nm CMOS. 280-281 - Yuichi Miyahara, Mitsuhiro Sano, Kazuo Koyama, Toshikazu Suzuki, Koichi Hamashita, Bang-Sup Song:
Adaptive cancellation of gain and nonlinearity errors in pipelined ADCs. 282-283 - Firat Yazicioglu, Taechan Kim:
Session 16 overview: Biomedical circuits & systems. 284-285 - Wei-Ming Chen, Herming Chiueh, Tsan-Jieh Chen, Chia-Lun Ho, Chi Jeng, Shun-Ting Chang, Ming-Dou Ker, Chun-Yu Lin, Ya-Chun Huang, Chia-Wei Chou, Tsun-Yuan Fan, Ming-Seng Cheng, Sheng-Fu Liang, Tzu-Chieh Chien, Sih-Yen Wu, Yu-Lin Wang, Fu-Zen Shaw, Yu-Hsing Huang, Chia-Hsiang Yang
A fully integrated 8-channel closed-loop neural-prosthetic SoC for real-time epileptic seizure control. 286-287 - Carolina Mora Lopez, Alexandru Andrei, Srinjoy Mitra, Marleen Welkenhuysen, Wolfgang Eberle, Carmen Bartic
An implantable 455-active-electrode 52-channel CMOS neural probe. 288-289 - Dong Han, Yuanjin Zheng, Ramamoorthy Rajkumar, Gavin Stewart Dawe, Minkyu Je:
A 0.45V 100-channel neural-recording IC with sub-µW/channel consumption in 0.18µm CMOS. 290-291 - Srinjoy Mitra, Jan Putzeys, Francesco Battaglia, Carolina Mora Lopez
24-channel dual-band wireless neural recorder with activity-dependent power consumption. 292-293 - Kuanfu Chen, Yi-Kai Lo, Wentai Liu:
A 37.6mm2 1024-channel high-compliance-voltage SoC for epiretinal prostheses. 294-295 - Manuel Monge, Mayank Raj, Meisam Honarvar Nazari, Jay Han-Chieh Chang, Yu Zhao, James D. Weiland
A fully intraocular 0.0169mm2/pixel 512-channel self-calibrating epiretinal prosthesis in 65nm CMOS. 296-297 - Andrew David Dehennis, Marko Mailand
A near-field-communication (NFC) enabled wireless fluorimeter for fully implantable biosensing applications. 298-299 - Constantine Sideris, Ali Hajimiri
An integrated magnetic spectrometer for multiplexed biosensing. 300-301 - Sunyoung Kim, Long Yan, Srinjoy Mitra, Masato Osawa, Yasunari Harada, Kosei Tamiya, Chris Van Hoof
A 20µW intra-cardiac signal-processing IC with 82dB bio-impedance measurement dynamic range and analog feature extraction for ventricular fibrillation detection. 302-303 - Yasuhiro Takai, James Sung:
Session 17 overview: High-performance DRAM interfaces. 304-305 - Kambiz Kaviani, Michael Bucher, Bruce Su, Barry Daly, Bill Stonecypher, Wayne D. Dettloff, Teva Stone, Kashinath Prabhu, Pravin Kumar Venkatesan, Fred Heaton, Ravi T. Kollipara, Yi Lu, Chris J. Madden, John C. Eble, Lei Luo, Nhat Nguyen:
A 6.4Gb/s near-ground single-ended transceiver for dual-rank DIMM memory interface systems. 306-307 - Soo-Min Lee, Jong-Hoon Kim, Jong-Sam Kim, Yunsaing Kim, Hyunbae Lee, Jae-Yoon Sim, Hong-June Park:
A 27% reduction in transceiver power for single-ended point-to-point DRAM interface with the termination resistance of 4×Z0 at both TX and RX. 308-309 - Marcel A. Kossel, Christian Menolfi, Thomas Toifl, Pier Andrea Francese
A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s thin-oxide DDR transmitter with 1.9-to-7.6V/ns clock-feathering slew-rate control in 22nm CMOS. 310-311 - Junyoung Song, Hyun-Woo Lee, Soo-Bin Lim, Sewook Hwang, Yunsaing Kim, Young-Jung Choi, Byong-Tae Chung, Chulwoo Kim:
An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface. 312-313 - Michael Clinton, Atsushi Kawasumi:
Session 18 overview: Advanced embedded SRAM. 314-315 - Jonathan Chang, Yen-Huei Chen, Hank Cheng, Wei-Min Chan, Hung-Jen Liao, Quincy Li, Stanley Chang, Sreedhar Natarajan, Robin Lee, Ping-Wei Wang, Shyue-Shyh Lin, Chung-Cheng Wu, Kuan-Lun Cheng, Min Cao, George H. Chang:
A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications. 316-317 - Mahmut E. Sinangil, Anantha P. Chandrakasan:
An SRAM using output prediction to reduce BL-switching activity and statistically-gated SA for up to 1.9× reduction in energy/access. 318-319 - Fumihiko Tachibana, Osamu Hirabayashi, Yasuhisa Takeyama, Miyako Shizuno, Atsushi Kawasumi, Keiichi Kushida, Azuma Suzuki, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe, Yasuo Unekawa:
A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit. 320-321 - Harold Pilo, Chad A. Adams, Igor Arsovski, Robert M. Houle, Steve Lamphier, Michael M. Lee, Frank Pavlik, Sushma N. Sambatur, Adnan Seferagic, Richard Wu, Mohammad Imran Younus:
A 64Mb SRAM in 22nm SOI technology featuring fine-granularity power gating and low-energy power-supply-partition techniques for 37% leakage reduction. 322-323 - John Davis, Paul Bunce, Diana M. Henderson, Yuen H. Chan, Uma Srinivasan, Daniel Rodko, Pradip Patel, Thomas J. Knips, Tobias Werner:
7GHz L1 cache SRAMs for the 32nm zEnterprise™ EC12 processor. 324-325 - Sven Mattisson, Koji Takinam:
Session 19 overview: Wireless transceivers for smart devices. 326-327 - Rakesh Kumar, T. Krishnaswamy, Gireesh Rajendran, Debapriya Sahu, Apu Sivadas, Murali Nandigam, Saravana Ganeshan, Srihari Datla, Anand Kudari, Hemant Bhasin, Meghna Agrawal, Subramanian Narayan, Yogesh Dharwekar, Robin Garg
A fully integrated 2×2 b/g and 1×2 a-band MIMO WLAN SoC in 45nm CMOS for multi-radio IC. 328-329 - Lu Ye, Jiashu Chen, Lingkai Kong, Philippe Cathelin, Elad Alon, Ali M. Niknejad:
A digitally modulated 2.4GHz WLAN transmitter with integrated phase path and dynamic load modulation in 65nm CMOS. 330-331 - Chao Lu, Hua Wang
A 24.7dBm all-digital RF transmitter for multimode broadband applications in 40nm CMOS. 332-333 - Chun-Geik Tan, Fei Song, Tieng Yi Choke, Ming Kong, De-Cheng Song, Chee-Hong Yong, Weimin Shu, Zong Hua You, Yi-Hsien Lin, Osama Shana'a
A universal GNSS (GPS/Galileo/Glonass/Beidou) SoC with a 0.25mm2 radio in 40nm CMOS. 334-335 - Lars Sundström
A receiver for LTE Rel-11 and beyond supporting non-contiguous carrier aggregation. 336-337 - Mark Ingels, Yoshikazu Furuta, Xiaoqiang Zhang, Sungwoo Cha, Jan Craninckx
A multiband 40nm CMOS LTE SAW-less modulator with -60dBc C-IM3. 338-339 - Paolo Rossi, Nicola Codega, Danilo Gerna, Antonio Liscidini
An LTE transmitter using a class-A/B power mixer. 340-341 - Jie-Wei Lai, Chi-Hsueh Wang, Kaipon Kao, Anson Lin, Yi-Hsien Cho, Lan-chou Cho, Meng-Hsiung Hung, Xin-Yu Shih
A 0.27mm2 13.5dBm 2.4GHz all-digital polar transmitter using 34%-efficiency Class-D DPA in 40nm CMOS. 342-343 - Marc Tiebout, Jing-Hong Conan Zhan:
Session 20 overview: Frequency generation. 344-345 - Luca Fanori, Pietro Andreani:
A 2.5-to-3.3GHz CMOS Class-D VCO. 346-347 - Masoud Babaie, Robert Bogdan Staszewski
Third-harmonic injection technique applied to a 5.87-to-7.56GHz 65nm CMOS Class-F oscillator with 192dBc/Hz FOM. 348-349 - Enrico Mammei, Enrico Monaco, Andrea Mazzanti, Francesco Svelto:
A 33.6-to-46.2GHz 32nm CMOS VCO with 177.5dBc/Hz minimum noise FOM using inductor splitting for tuning extension. 350-351 - Wanghua Wu, Xuefei Bai, Robert Bogdan Staszewski
A 56.4-to-63.4GHz spurious-free all-digital fractional-N PLL in 65nm CMOS. 352-353 - Xiang Yi, Chirn Chye Boon
A 57.9-to-68.3GHz 24.6mW frequency synthesizer with in-phase injection-coupled QVCO in 65nm CMOS. 354-355 - Roberto Nonis, Werner Grollitsch, Thomas Santa, Dmytro Cherniak, Nicola Da Dalt:
A 2.4psrms-jitter digital PLL with Multi-Output Bang-Bang Phase Detector and phase-interpolator-based fractional-N divider. 356-357 - Zhangwen Tang, Xiongxiong Wan, Minggui Wang, Jie Liu:
A 50-to-930MHz quadrature-output fractional-N frequency synthesizer with 770-to-1860MHz single-inductor LC-VCO and without noise folding effect for multistandard DTV tuners. 358-359 - Wing-Hung Ki
Session 21 overview: Power converters. 360-361 - Cheng Huang
An 82.4% efficiency package-bondwire-based four-phase fully integrated buck converter with flying capacitor for area reduction. 362-363 - Patrick Riehl, Paul Fowers, Hao-Ping Hong, Michael Ashburn:
An AC-coupled hybrid envelope modulator for HSUPA transmitters with 80% modulator efficiency. 364-365 - Muhammad Hassan, Peter M. Asbeck, Lawrence E. Larson:
A CMOS dual-switching power-supply modulator with 8% efficiency improvement for 20MHz LTE Envelope Tracking RF power amplifiers. 366-367 - Saurav Bandyopadhyay, Bob Neidorff, Dave Freeman, Anantha P. Chandrakasan:
90.6% efficient 11MHz 22W LED driver using GaN FETs and burst-mode controller with 0.96 power factor. 368-369 - Suyoung Bang, Allan Wang, Bharan Giridhar, David T. Blaauw, Dennis Sylvester:
A fully integrated successive-approximation switched-capacitor DC-DC converter with 31mV output voltage resolution. 370-371 - Hanh-Phuc Le
A sub-ns response fully integrated battery-connected switched-capacitor voltage regulator delivering 0.19W/mm2 at 73% efficiency. 372-373 - Dina El-Damak
A 93% efficiency reconfigurable switched-capacitor DC-DC converter using on-chip ferroelectric capacitors. 374-375 - Junsik Kim, Jiyong Lee, Shihong Park:
A soft self-commutating method using minimum control circuitry for multiple-string LED drivers. 376-377 - Aaron Partridge, Young-Sun Na:
Session 22 overview: Sensors & displays. 378-379 - Vladimir P. Petkov, Ganesh K. Balachandran, Jochen Beintner:
A fully differential charge-balanced accelerometer for Electronic Stability Control. 380-381 - Selcuk Ersoy, Robert H. M. van Veldhoven, Fabio Sebastiano
A 0.25mm2 AC-biased MEMS microphone interface with 58dBA SNR. 382-383 - Mohammad Alhawari
A 0.5V <4µW CMOS photoplethysmographic heart-rate sensor IC based on a non-uniform quantizer. 384-385 - Saleh Heidary Shalmany, Dieter Draxelmayr, Kofi A. A. Makinwa:
A micropower battery current sensor with ±0.03% (3σ) inaccuracy from -40 to +85°C. 386-387 - Hyungcheol Shin, Seunghoon Ko, Hongjae Jang, Ilhyun Yun, Kwyro Lee:
A 55dB SNR with 240Hz frame scan rate mutual capacitor 30×24 touch-screen panel read-out IC using code-division multiple sensing technique. 388-389 - Junhyeok Yang, Sang-Hui Park, Jung-Min Choi, Hyunsik Kim, Changbyung Park, Seung-Tak Ryu, Gyu-Hyeong Cho:
A highly noise-immune touch controller using Filtered-Delta-Integration and a charge-interpolation technique for 10.1-inch capacitive touch-screen panels. 390-391 - Hyunsik Kim, Junhyeok Yang, Sang-Hui Park, Seung-Tak Ryu, Gyu-Hyeong Cho:
A 5.6mV inter-channel DVO 10b column-driver IC with mismatch-free switched-capacitor interpolation for mobile active-matrix LCDs. 392-393 - Bertrand Dupont, Antoine Dupret, Sebastien Becker, Antoine Hamelin, Fabrice Guellec
A [10°C; 70°C] 640×480 17µm pixel pitch TEC-less IR bolometer imager with below 50mK and below 4V power supply. 394-395 - Anshuman Bhuyan, Jung Woo Choe, Byung-chul Lee
3D volumetric ultrasound imaging with a 32×32 CMUT array integrated with front-end ICs using flip-chip bonding technology. 396-397 - Gerrit den Besten, Koichi Yamaguchi:
Session 23 overview: Short-reach links, XCVR techniques, & PLLs. 398-399 - Yong Liu, Ping-Hsuan Hsieh
A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI. 400-401 - Mozhgan Mansuri, James E. Jaussi, Joseph T. Kennedy, Tzu-Chien Hsueh, Sudip Shekhar, Ganesh Balamurugan, Frank O'Mahony, Clark Roberts, Randy Mooney, Bryan Casper:
A scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-lane parallel I/O in 32nm CMOS. 402-403 - John W. Poulton, William J. Dally, Xi Chen, John G. Eyles, Thomas H. Greer, Stephen G. Tell, C. Thomas Gray:
A 0.54pJ/b 20Gb/s ground-referenced single-ended short-haul serial link in 28nm CMOS for advanced packaging applications. 404-405 - Ken'ichiro Hijioka, Masaharu Matsudaira, Koichi Yamaguchi, Masayuki Mizuno:
A 5.5Gb/s 5mm contactless interface containing a 50Mb/s bidirectional sub-channel employing common-mode OOK signaling. 406-407 - Marcel A. Kossel, Thomas Toifl, Pier Andrea Francese
An 8Gb/s 1.5mW/Gb/s 8-tap 6b NRZ/PAM-4 Tomlinson-Harashima precoding transmitter for future memory-link applications in 22nm CMOS. 408-409 - Ji-Hwan Seol, Young-Ju Kim, Sang-Hye Chung, Kyung-Soo Ha, Seung-Jun Bae, Jung-Bae Lee, Joo-Sun Choi, Lee-Sup Kim:
An 8Gb/s 0.65mW/Gb/s forwarded-clock receiver using an ILO with dual feedback loop and quadrature injection scheme. 410-411 - Kanupriya Bhardwaj, Sriram Narayan, Sergey Y. Shumarayev, Thomas H. Lee:
A 3.1mW phase-tunable quadrature-generation method for CEI 28G short-reach CDR in 28nm CMOS. 412-413 - I-Ting Lee, Yen-Jen Chen, Shen-Iuan Liu, Chewnpu Jou, Fu-Lung Hsueh, Hsieh-Hung Hsieh:
A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing. 414-415 - Tsung-Kai Kao, Che-Fu Liang, Hsien-Hsiang Chiu, Michael Ashburn:
A wideband fractional-N ring PLL with fractional-spur suppression using spectrally shaped segmentation. 416-417 - Wim Dehaene, Masaya Sumita:
Session 24 overview: Energy-aware digital design. 418-419 - Daisuke Miyashita, Ryo Yamaki, Kazunori Hashiyoshi, Hiroyuki Kobayashi, Shouhei Kousai, Yukihito Oowaki, Yasuo Unekawa:
A 10.4pJ/b (32, 8) LDPC decoder with time-domain analog and digital mixed-signal processing. 420-421 - Youn Sung Park, Yaoyu Tao, Zhengya Zhang
A 1.15Gb/s fully parallel nonbinary LDPC decoder with fine-grained dynamic clock gating. 422-423 - Philippe Flatresse, Bastien Giraud, Jean-Philippe Noel, Bertrand Pelloux-Prayer, Fabien Giner, Deepak-Kumar Arora, Franck Arnaud, Nicolas Planes, Julien Le Coz, Olivier Thomas, Sylvain Engels, Giorgio Cesana, Robin Wilson, Pascal Urard:
Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology. 424-425 - Jian-Shiun Chen, Chingwei Yeh, Jinn-Shyan Wang:
Self-super-cutoff power gating with state retention on a 0.3V 0.29fJ/cycle/gate 32b RISC core in 0.13µm CMOS. 426-427 - Paul N. Whatmough, Shidhartha Das, David M. Bull:
A low-power 1GHz razor FIR accelerator with time-borrow tracking pipeline and approximate error correction in 65nm CMOS. 428-429 - Mario Konijnenburg, Yeon-Gon Cho, Maryam Ashouei, Tobias Gemmeke, Changmoo Kim, Jos Hulzink, Jan Stuyt, Mookyung Jung, Jos Huisken, Soojung Ryu, Jungwook Kim, Harmke de Groot:
Reliable and energy-efficient 1MHz 0.4V dynamically reconfigurable SoC for ExG applications in 40nm LP CMOS. 430-431 - Steven Bartling, Sudhanshu Khanna, Michael Clinton, Scott R. Summerfelt, John A. Rodriguez, Hugh P. McAdams:
An 8MHz 75µA/MHz zero-leakage non-volatile logic-based Cortex-M0 MCU SoC exhibiting 100% digital state retention at VDD=0V with <400ns wakeup and sleep transitions. 432-433 - Satoshi Takaya, Makoto Nagata
A 100GB/s wide I/O with 4096b TSVs through an active silicon interposer with in-place waveform capturing. 434-435 - Hiroshi Fuketa, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai:
Intermittent resonant clocking enabling power reduction at any clock frequency for 0.37V 980kHz near-threshold logic circuits. 436-437 - Shouhei Kousai, Gangadhar Burra:
Session 25 overview: Energy-efficient wireless. 438-439 - Yogesh Darwhekar, Evgeniy Braginskiy, Koby Levy, Abhishek Agrawal, Vikas Singh, Ronen Issac, Ofer Blonskey, Ofer Adler, Yoav Benkuzari, Matan Ben-Shachar, Srikanth Manian, Apu Sivadas, Subhashish Mukherjee, Gangadhar Burra, Nir Tal, Yariv Shlivinski, Guy Bitton, Sreekiran Samala:
A 45nm CMOS near-field communication radio with 0.15A/m RX sensitivity and 4mA current consumption in card emulation mode. 440-441 - Jonathan K. Brown, Kuo-Ken Huang, Elnaz Ansari, Ryan R. Rogel, Yoonmyung Lee
An ultra-low-power 9.8GHz crystal-less UWB transceiver with digital baseband integrated in 0.18µm BiCMOS. 442-443 - Baradwaj Vigraham, Peter R. Kinget
A self-duty-cycled and synchronized UWB receiver SoC consuming 375pJ/b for -76.5dBm sensitivity at 2Mb/s. 444-445 - Yao-Hong Liu
A 1.9nJ/b 2.4GHz multistandard (Bluetooth Low Energy/Zigbee/IEEE802.15.6) transceiver for personal/body-area networks. 446-447 - Zhicheng Lin, Pui-In Mak
A 1.7mW 0.22mm2 2.4GHz ZigBee RX exploiting a current-reuse blixer + hybrid filter topology in 65nm CMOS. 448-449 - San-Jeow Cheng, Yuan Gao
A 110pJ/b multichannel FSK/GMSK/QPSK/p/4-DQPSK transmitter with phase-interpolated dual-injection DLL-based synthesizer employing hybrid FIR. 450-451 - Hyungwoo Lee, Kwonjoon Lee, Sunjoo Hong, Kiseok Song, Taehwan Roh
A 5.5mW IEEE-802.15.6 wireless body-area-network standard transceiver for multichannel electro-acupuncture application. 452-453 - Jan van Sinderen, Gerben W. de Jong, Frank Leong, Xin He, Melina Apostolidou, Harish Kundur Subramaniyan, Robert Rutten, Jan Niehof, Jos Verlinden, Hao Wang, Anton Hoogstraate, Ka Chun Kwok, Rene Verlinden, Reinier Hoogendoorn, Dennis Jeurissen, Anton Salfelner, Ewald Bergler, Javier M. Velandia Torres, Christopher J. Haji-Michael, Thomas Unterweger, Esa Tarvainen, Martin Posch
Wideband UHF ISM-band transceiver supporting multichannel reception and DSSS modulation. 454-455 - Fan Zhang, Keping Wang, Jabeom Koo
A 1.6mW 300mV-supply 2.4GHz receiver with -94dBm sensitivity for energy-harvesting applications. 456-457 - Liechao Huang, Warren Rieutort-Louis, Yingzhe Hu, Josue Sanz-Robinson, Sigurd Wagner, James C. Sturm, Naveen Verma:
A super-regenerative radio on plastic based on thin-film transistors and antennas on large flexible sheets for distributed communication links. 458-459 - Boris Murmann, Tetsuya Iizuka:
Session 26 overview: High-speed data converters. 460-461 - Shwetabh Verma, Athos Kasapi, Li-min Lee, Dean Liu, Dimitri Loizos, Song-Hee Paik, Aida Varzaghani, Sotirios Zogopoulos, Stefanos Sidiropoulos:
A 10.3GS/s 6b flash ADC for 10G Ethernet applications. 462-463 - Erwin Janssen, Kostas Doris, Athon Zanikopoulos, Alessandro Murroni, Gerard van der Weide, Yu Lin, Ludo Alvado, Frederic Darthenay, Yannick Fregeais:
An 11b 3.6GS/s time-interleaved SAR ADC in 65nm CMOS. 464-465 - Brian Setterberg, Ken Poulton, Sourja Ray, Dan J. Huber, Valentin Abramzon, Guenter Steinbach, John P. Keane, Bernd Wuppermann, Mathew Clayson, Matthew Martin, Rizwan Pasha, Edda Peeters, Annemie Jacobs, Filip Demarsin, Adnan Al-Adnani, Peter Brandt:
A 14b 2.5GS/s 8-way-interleaved pipelined ADC with background calibration and digital dynamic linearity correction. 466-467 - Lukas Kull, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese
A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS. 468-469 - Hyeok-Ki Hong, Hyun-Wook Kang, Barosaim Sung, Choong-Hoon Lee, Michael Choi, Ho-Jin Park, Seung-Tak Ryu:
An 8.6 ENOB 900MS/s time-interleaved 2b/cycle SAR ADC with a 1b/cycle reconfiguration for resolution enhancement. 470-471 - Ron Kapusta
A 14b 80MS/s SAR ADC with 73.6dB SNDR in 65nm CMOS. 472-473 - Wei-Te Lin, Tai-Haur Kuo:
A 12b 1.6GS/s 40mW DAC in 40nm CMOS with >70dB SFDR over entire Nyquist bandwidth. 474-475 - Robert Johansson, Shoji Kawahito:
Session 27 overview: Image sensors. 476-477 - Jaehyuk Choi, Seokjun Park, Jihyun Cho, Euisik Yoon:
A 3.4µW CMOS image sensor with embedded feature-extraction algorithm for motion-triggered object-of-interest imaging. 478-479 - Gyouho Kim, Mahmood Barangi, Zhiyoong Foo, Nathaniel Ross Pinckney, Suyoung Bang, David T. Blaauw, Dennis Sylvester:
A 467nW CMOS visual motion sensor with temporal averaging and pixel aggregation. 480-481 - Jun Aoki, Yoshiaki Takemoto, Kenji Kobayashi, Naofumi Sakaguchi, Mitsuhiro Tsukimura, Naohiro Takazawa, Hideki Kato, Toru Kondo, Haruhisa Saito, Yuichi Gomi, Yoshitaka Tadaki:
A rolling-shutter distortion-free 3D stacked image sensor with -160dB parasitic light sensitivity in-pixel storage node. 482-483 - Shunichi Sukegawa, Taku Umebayashi, Tsutomu Nakajima, Hiroshi Kawanobe, Ken Koseki, Isao Hirota, Tsutomu Haruta, Masanori Kasai, Koji Fukumoto, Toshifumi Wakano, Keishi Inoue, Hiroshi Takahashi, Takashi Nagano, Yoshikazu Nitta, Teruo Hirayama, Noriyuki Fukushima:
A 1/4-inch 8Mpixel back-illuminated stacked CMOS image sensor. 484-485 - Leo Huf Campos Braga, Leonardo Gasparini
An 8×16-pixel 92kSPAD time-resolved sensor with on-pixel 64ps 12b TDC and 100MS/s real-time energy histogramming in 0.13µm CIS technology for PET/MRI applications. 486-487 - Cristiano Niclass, Mineki Soga, Hiroyuki Matsubara, Masaru Ogawa, Manabu Kagami:
A 0.18µm CMOS SoC for a 100m-range 10fps 200×96-pixel time-of-flight depth sensor. 488-489 - Olga Shcherbakova, Lucio Pancheri
3D camera based on linear-mode gain-modulated avalanche photodiodes. 490-491 - Shinzo Koyama, Kazutoshi Onozawa, Keisuke Tanaka, Yoshihisa Kato:
A 3D vision 2.1Mpixel image sensor for single-lens camera systems. 492-493 - Jun Deguchi, Fumihiko Tachibana, Makoto Morimoto, Masayoshi Chiba, Takeshi Miyaba, Hideki Tanaka, Kyoichi Takenaka, Satoshi Funayama, Kunihiko Amano, Kazuhide Sugiura, Ryuta Okamoto, Shouhei Kousai:
A 187.5µVrms-read-noise 51mW 1.4Mpixel CMOS image sensor with PMOSCAP column CDS and 10b self-differential offset-cancelled pipeline SAR-ADC. 494-495 - Albert C. Jerng, Yorgos Palaskas, Eric A. M. Klumperink, Didier Belot, Songcheol Hong, Brian A. Floyd:
F1: Advanced RF transceiver design techniques. 500-501 - Leland Chang, Shannon Morton, Ken Chang, Jin-Man Han, Piero Malcovati, Vladimir Stojanovic:
F2: VLSI power-management techniques: Principles and applications. 502-503 - Elad Alon, Azita Emami, Gerrit den Besten, Ichiro Fujimori, Tadahiro Kuroda, Masafumi Nogawa, Hisakatsu Yamaguchi:
F3: Emerging technologies for wireline communication. 504-505 - Makoto Ikeda, Ehsan Afshari, Yusuke Oike, David Ruffieux, Johannes Solhusvik, Albert Theuwissen:
F4: Scientific imaging. 506-507 - Antonio Liscidini, SeongHwan Cho, Tony Chan Carusone, Tanay Karnik, Mike Keaveney, Brian Otis, Aaron Partridge, Christoph Sandner:
F5: Frequency generation and clock distribution. 508-509 - Boris Murmann, Jafar Savoj, Piet Wambacq, Jieh-Tsorng Wu:
F6: Mixed-signal/RF design and modeling in next-generation CMOS. 510-511 - Jan Van der Spiegel:
ES1: Student research preview. 512 - Minkyu Je, Axel Thomsen:
ES2: "batteries not included." - How little is enough for real energy autonomy? 513 - Trudy Stetzler, Anantha P. Chandrakasan, Bram Nauta:
EP1: Antiques from the innovations attic. 514 - Nicola Da Dalt, Ajith Amerasekera:
ES3: High-speed communications on 4 wheels: What's in your next car? 515 - Michael P. Flynn, John Khoury:
EP2: You're hired! The top 25 interview questions for circuit designers. 516 - Shekhar Borkar, Uming Ko, Ali Keshavarzi, Eugenio Cantatore:
EP3: Empowering the killer SoC applications of 2020. 517 - Willy Sansen, Hooman Darabi, John R. Long, Ali Hajimiri, Ali M. Niknejad:
RF blocks for wireless transceivers. 518 - Bram Nauta, Trudy Stetzler:
International technical program committee. 525-526
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