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IEEE Transactions on Very Large Scale Integration Systems, Volume 25
Volume 25, Number 1, January 2017
- Krishnendu Chakrabarty
, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho
Editorial. 1-20 - Nuno Miguel Cardanha Paulino
Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces. 21-34 - Muhammad Umar Karim Khan
EBSCam: Background Subtraction for Ubiquitous Computing. 35-47 - Azadeh Alsadat Emrani Zarandi, Amir Sabbagh Molahosseini
An Efficient Component for Designing Signed Reverse Converters for a Class of RNS Moduli Sets of Composite Form {2k, 2P-1}. 48-59 - Enyi Yao
VLSI Extreme Learning Machine: A Design Space Exploration. 60-74 - Saeid Gorgin
Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication. 75-86 - Jun Lin, Zhiyuan Yan, Zhongfeng Wang:
Efficient Soft Cancelation Decoder Architectures for Polar Codes. 87-99 - Jon J. Pimentel
Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs. 100-113 - Poki Chen
A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter Based on Delay Wrapping and Averaging. 114-124 - Munehiro Kozuma, Yuki Okamoto, Takashi Nakagawa, Takeshi Aoki, Yoshiyuki Kurokawa, Takayuki Ikeda, Yoshinori Ieda, Naoto Yamade, Hidekazu Miyairi, Makoto Ikeda, Masahiro Fujita, Shunpei Yamazaki:
Subthreshold Operation of CAAC-IGZO FPGA by Overdriving of Programmable Routing Switch and Programmable Power Switch. 125-138 - Bo-Cheng Charles Lai
Efficient Designs of Multiported Memory on FPGA. 139-150 - Marco Rabozzi, Gianluca Carlo Durelli, Antonio Miele
Floorplanning Automation for Partial-Reconfigurable FPGAs via Feasible Placements Generation. 151-164 - Zia Uddin Ahamed Khan, Mohammed Benaissa
High-Speed and Low-Latency ECC Processor Implementation Over GF(2m) on FPGA. 165-176 - Wenchao Qian
ENFIRE: A Spatio-Temporal Fine-Grained Reconfigurable Hardware. 177-188 - Joao Pedro Cerqueira
Temporarily Fine-Grained Sleep Technique for Near- and Subthreshold Parallel Architectures. 189-197 - Alireza Mahzoon, Bijan Alizadeh
OptiFEX: A Framework for Exploring Area-Efficient Floating Point Expressions on FPGAs With Optimized Exponent/Mantissa Widths. 198-209 - Erfan Azarkhish
Logic-Base Interconnect Design for Near Memory Computing in the Smart Memory Cube. 210-223 - Ahmad T. Sheikh
A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor Redundancy. 224-237 - Martin Omaña
Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST. 238-246 - Mohsen Raji
Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in the Presence of Process Variations. 247-260 - Mina A. Farhan
Parallel High-Order Envelope-Following Method for Fast Transient Analysis of Highly Oscillatory Circuits. 261-270 - Seongbo Shim
Lithography Defect Probability and Its Application to Physical Design Optimization. 271-285 - Albert Ciprut
Modeling Size Limitations of Resistive Crossbar Array With Cell Selectors. 286-293 - Marvin Damschen
Timing Analysis of Tasks on Runtime Reconfigurable Processors. 294-307 - Saikat Mondal
Modeling and Crosstalk Evaluation of 3-D TSV-Based Inductor With Ground TSV Shielding. 308-318 - Xiaoliang Dai
Improving Convergence and Simulation Time of Quantum Hydrodynamic Simulation: Application to Extraction of Best 10-nm FinFET Parameter Values. 319-329 - Edoardo Fusella
H2ONoC: A Hybrid Optical-Electronic NoC Based on Hybrid Topology. 330-343 - Junyoung Song, Hyun-Woo Lee, Sewook Hwang, Chulwoo Kim
A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique. 344-353 - Yan Zhu
A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations. 354-363 - Arshad Hussain
Active-Passive ΔΣ Modulator for High-Resolution and Low-Power Applications. 364-374 - Mario Garrido
A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices. 375-379 - Taeho Lee
A 5-Gb/s Digital Clock and Data Recovery Circuit With Reduced DCO Supply Noise Sensitivity Utilizing Coupling Network. 380-384 - Mohammed Zackriya V
Content Addressable Memory - Early Predict and Terminate Precharge of Match-Line. 385-387 - Archit Joshi
Nonlinearity Estimation for Compensation of Phase Interpolator in Bang-Bang CDRs. 388-392
Volume 25, Number 2, February 2017
- Reza Zendegani, Mehdi Kamal, Milad Bahadori, Ali Afzali-Kusha
RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing. 393-401 - Kwen-Siong Chong, Weng-Geng Ho
Sense Amplifier Half-Buffer (SAHB) A Low-Power High-Performance Asynchronous Logic QDI Cell Template. 402-415 - Srikar Bhagavatula
Variation Resilient Power Sensor With an 80-ns Response Time for Fine-Grained Power Management. 416-426 - Amir M. Rahmani
Reliability-Aware Runtime Power Management for Many-Core Systems in the Dark Silicon Era. 427-440 - Shoaleh Hashemi Namin
Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique. 441-449 - Sundarrajan Rangachari
Scenario-Aware Dynamic Power Reduction Using Bias Addition. 450-461 - Arnab Raha
Energy-Efficient Reduce-and-Rank Using Input-Adaptive Approximations. 462-475 - Hooman Farkhani
STT-RAM Energy Reduction Using Self-Referenced Differential Write Termination Technique. 476-487 - Chien-Chung Ho, Yu-Ping Liu, Yuan-Hao Chang
Antiwear Leveling Design for SSDs With Hybrid ECC Capability. 488-501 - Robert Giterman
Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications. 502-509 - Chihiro Matsui
Write Order-Based Garbage Collection Scheme for an LBA Scrambler Integrated SSD. 510-519 - Naifeng Jing, Shunning Jiang, Shuang Chen, Jingjie Zhang, Li Jiang, Chao Li, Xiaoyao Liang:
Bank Stealing for a Compact and Efficient Register File Architecture in GPGPU. 520-533 - Nishit Ashok Kapadia, Sudeep Pasricha
A Runtime Framework for Robust Application Scheduling With Adaptive Parallelism in the Dark-Silicon Era. 534-546 - Reiley Jeyapaul
Systematic Methodology for the Quantitative Analysis of Pipeline-Register Reliability. 547-555 - Zhonghai Lu
Dynamic Traffic Regulation in NoC-Based Systems. 556-569 - Kamran Rahmani
Postsilicon Trace Signal Selection Using Machine Learning Techniques. 570-580 - Shao-Yun Fang
Cut Mask Optimization With Wire Planning in Self-Aligned Multiple Patterning Full-Chip Routing. 581-593 - Artjom Grudnitsky
Efficient Partial Online Synthesis of Special Instructions for Reconfigurable Processors. 594-607 - Itamar Levi
CPA Secured Data-Dependent Delay-Assignment Methodology. 608-620 - I-Jen Chao
Analyses of Splittable Amplifier Technique and Cancellation of Memory Effect for Opamp Sharing. 621-634 - Massoud Tohidian
A Fully Integrated Discrete-Time Superheterodyne Receiver. 635-647 - Isaak Yang, Sung Hoon Jung, Kwang-Hyun Cho
Self-Repairing Digital System Based on State Attractor Convergence Inspired by the Recovery Process of a Living Cell. 648-659 - Randy W. Mann
Bias-Induced Healing of $V_{\text {min}}$ Failures in Advanced SRAM Arrays. 660-669 - Zhan-Hui Li
Eliminating Timing Errors Through Collaborative Design to Maximize the Throughput. 670-682 - Yingnan Cui
A Variation-Aware Adaptive Fuzzy Control System for Thermal Management of Microprocessors. 683-695 - Michael Cheah, Debashis Mandal
A 100-mA, 99.11% Current Efficiency, 2-mVpp Ripple Digitally Controlled LDO With Active Ripple Suppression. 696-704 - Ata Khorami
An Efficient Fast Switching Procedure for Stepwise Capacitor Chargers. 705-713 - Jian-Bin Zhou
A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding. 714-724 - Pingxiuqi Chen, Shaik Nazeem Basha, Mehran Mozaffari Kermani
FPGA Realization of Low Register Systolic All-One-Polynomial Multipliers Over $GF(2^{m})$ and Their Applications in Trinomial Multipliers. 725-734 - Chiou-Yng Lee
Low-Complexity Digit-Serial Multiplier Over $GF(2^{m})$ Based on Efficient Toeplitz Block Toeplitz Matrix-Vector Product Decomposition. 735-746 - Zhiheng Wang
Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map. 747-759 - Moon Gi Seok, Tag Gon Kim, Chang Beom Choi, Daejin Park
An HLA-Based Distributed Cosimulation Framework in Mixed-Signal System-on-Chip Design. 760-764 - Leonardo Rezende Juracy
Optimized Design of an LSSD Scan Cell. 765-768 - Hailang Wang, Emre Salman
Closed-Form Expressions for I/O Simultaneous Switching Noise Revisited. 769-773 - Derui Kong
Analysis and Reduction of Nonidealities in Stacked-Transistor Current Sources. 774-778 - Ji-Hoon Park, Hyun-Seung Seo, Bai-Sun Kong
Conditional-Boosting Flip-Flop for Near-Threshold Voltage Application. 779-782 - Chung-Shiang Wu, Hui-Hsuan Lee, Po-Hung Chen
Digital Buck Converter With Switching Loss Reduction Scheme for Light Load Efficiency Enhancement. 783-787 - Kihwan Seong, Won-Cheol Lee, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
All-Synthesizable Current-Mode Transmitter Driver for USB2.0 Interface. 788-792
Volume 25, Number 3, March 2017
- Jungwoo Park
A Way-Filtering-Based Dynamic Logical-Associative Cache Architecture for Low-Energy Consumption. 793-805 - Mengshuo Wang
High-Dimensional and Multiple-Failure-Region Importance Sampling for SRAM Yield Analysis. 806-819 - Yen-Hao Chen
A Novel Cache-Utilization-Based Dynamic Voltage-Frequency Scaling Mechanism for Reliability Enhancements. 820-832 - Menglong Guan, Lei Wang
Improving DRAM Performance in 3-D ICs via Temperature Aware Refresh. 833-843 - Jooyoung Kim, Woosung Lee, Keewon Cho, Sungho Kang
Hardware-Efficient Built-In Redundancy Analysis for Memory With Various Spares. 844-856 - Alejandro Valero
On Microarchitectural Mechanisms for Cache Wearout Reduction. 857-871 - Yang Xu
A Flexible Continuous-Time Δ Σ ADC With Programmable Bandwidth Supporting Low-Pass and Complex Bandpass Architectures. 872-880 - Je-Kwang Cho
A 92-dB DR, 24.3-mW, 1.25-MHz BW Sigma-Delta Modulator Using Dynamically Biased Op Amp Sharing. 881-893 - Babak Zamanlooy
An Analog CVNS-Based Sigmoid Neuron for Precise Neurochips. 894-906 - Qing Dong
Low-Power and Compact Analog-to-Digital Converter Using Spintronic Racetrack Memory Devices. 907-918 - Nashiru Alhassan
An All-MOSFET Sub-1-V Voltage Reference With a - 51 -dB PSR up to 60 MHz. 919-928 - Zhao Zhang
A 2.4-3.6-GHz Wideband Subharmonically Injection-Locked PLL With Adaptive Injection Timing Alignment Technique. 929-941 - Dong Xiang
Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding. 942-953 - Saba Amanollahi, Ghassem Jaberipur
Energy-Efficient VLSI Realization of Binary64 Division With Redundant Number Systems. 954-961 - Hsiang-Jen Tsai
Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology. 962-973 - Swaminathan Narayanaswamy
Modular Active Charge Balancing for Scalable Battery Packs. 974-987 - David Cavalheiro
Insights Into Tunnel FET-Based Charge Pumps and Rectifiers for Energy Harvesting Applications. 988-997 - Ahmed Awad
A Fast Process-Variation-Aware Mask Optimization Algorithm With a Novel Intensity Modeling. 998-1011 - Nezam Rohbani, Mojtaba Ebrahimi, Seyed Ghassem Miremadi
Bias Temperature Instability Mitigation via Adaptive Cache Size Management. 1012-1022 - Myat Thu Linn Aung, Takefumi Yoshikawa, Chuan Seng Tan
Yield Enhancement of Face-to-Face Cu-Cu Bonding With Dual-Mode Transceivers in 3DICs. 1023-1031 - Wei Jin
In Situ Error Detection Techniques in Ultralow Voltage Pipelines: Analysis and Optimizations. 1032-1043 - Immanuel Raja
A 0.1-2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits in 130-nm CMOS. 1044-1053 - Riadul Islam
CMCS: Current-Mode Clock Synthesis. 1054-1062 - Chandra Babu Dara
Delay Analysis for Current Mode Threshold Logic Gate Designs. 1063-1071 - Ayesha Khalid, Goutam Paul
RC4-AccSuite: A Hardware Acceleration Suite for RC4-Like Stream Ciphers. 1072-1084 - Fatemeh Tehranipoor
DRAM-Based Intrinsic Physically Unclonable Functions for System-Level Security and Authentication. 1085-1097 - Syed Mohsin Abbas
High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder. 1098-1111 - Grzegorz Mrugalski, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer
Trimodal Scan-Based Test Paradigm. 1112-1125 - Karthi Duraisamy, Yuankun Xue, Paul Bogdan, Partha Pratim Pande
Multicast-Aware High-Performance Wireless Network-on-Chip Architectures. 1126-1139 - Cong Hao
Interconnection Allocation Between Functional Units and Registers in High-Level Synthesis. 1140-1153 - S. Rasool Hosseini, Mehdi Saberi
A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications. 1154-1158 - Guanghui Hu, Jin Sha
High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations. 1159-1163 - Fengjuan Wang
An Ultracompact Butterworth Low-Pass Filter Based on Coaxial Through-Silicon Vias. 1164-1167 - Dezhi Xing
Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial $V_{\mathrm {cm}}$ -Based Switching. 1168-1172 - Doron Gluzer, Shmuel Wimer
Probability-Driven Multibit Flip-Flop Integration With Clock Gating. 1173-1177 - Jaewon Jang, Minho Cheong, Jin-Ho Ahn, Sung Kyu Lim
Chain-Based Approach for Fast Through-Silicon-Via Coupling Delay Estimation. 1178-1182 - Tae Woo Oh, Hanwool Jeong, Kyoman Kang, Juhyun Park, Younghwi Yang, Seong-Ook Jung
Power-Gated 9T SRAM Cell for Low-Energy Operation. 1183-1187 - Bin Zhang
Hardware Implementation for Real-Time Haze Removal. 1188-1192
Volume 25, Number 4, April 2017
- Naeem Maroof
10T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage. 1193-1203 - Raf Appeltans
A Smaller, Faster, and More Energy-Efficient Complementary STT-MRAM Cell Uses Three Transistors and a Ground Grid: More Is Actually Less. 1204-1214 - Donkyu Baek, Naehyuck Chang, Donghwa Shin
Compressed On-Chip Framebuffer Cache for Low-Power Display Systems. 1215-1223 - Fernando García-Redondo
Reconfigurable Writing Architecture for Reliable RRAM Operation in Wide Temperature Ranges. 1224-1235 - Ju Hee Choi
Fast Writeable Block-Aware Cache Update Policy for Spin-Transfer-Torque RAM. 1236-1249 - Peter G. Sarson
Fast Bit Screening of Automotive Grade EEPROMs - Continuous Improvement Exercise. 1250-1260 - Abdul Hafiz Alameh
A 0.13-µm CMOS Dynamically Reconfigurable Charge Pump for Electrostatic MEMS Actuation. 1261-1270 - Sae Kyu Lee
A 16-Core Voltage-Stacked System With Adaptive Clocking and an Integrated Switched-Capacitor DC-DC Converter. 1271-1284 - Lili Song, Ying Wang
STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator. 1285-1296 - Xiaoyin Bai
A High-Efficiency 6.78-MHz Full Active Rectifier With Adaptive Time Delay Control for Wireless Power Transmission. 1297-1306 - Chio-In Ieong, Mingzhong Li, Man-Kay Law, Pui-In Mak
A 0.45 V 147-375 nW ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation Architectures. 1307-1319 - Mahmoud Méribout
A Pipelined Parallel Hardware Architecture for 2-D Real-Time Electrical Capacitance Tomography Imaging Using Interframe Correlation. 1320-1328 - Yufeng Tong
Compiler-Guided Parallelism Adaption Based on Application Partition for Power-Gated ILP Processor. 1329-1341 - Xinmiao Zhang
Low-Complexity Transformed Encoder Architectures for Quasi-Cyclic Nonbinary LDPC Codes Over Subfields. 1342-1351 - Omid Akbari
Dual-Quality 4: 2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers. 1352-1361 - Weijing Shi
An FPGA-Based Hardware Accelerator for Traffic Sign Detection. 1362-1372 - Dong Wang
A 65-nm CMOS Constant Current Source With Reduced PVT Variation. 1373-1385 - Pil-Ho Lee
An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock. 1386-1396 - Vasileios Tenentes
Coarse-Grained Online Monitoring of BTI Aging by Reusing Power-Gating Infrastructure. 1397-1407 - Reza Ramezani
Reliability Improvement of Hardware Task Graphs via Configuration Early Fetch. 1408-1420 - Rajendra Bishnoi
Design of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-Flops. 1421-1432 - Jie Guo
Data-Pattern-Aware Error Prevention Technique to Improve System Reliability. 1433-1443 - Innocent Agbo
Integral Impact of BTI, PVT Variation, and Workload on SRAM Sense Amplifier. 1444-1454 - Hiromitsu Awano
Scalable Device Array for Statistical Characterization of BTI-Related Parameters. 1455-1466 - Manjari Pradhan
COMEDI: Combinatorial Election of Diagnostic Vectors From Detection Test Sets for Logic Circuits. 1467-1476 - Yun-Jui Li, Ching-Yi Huang, Chia-Cheng Wu
Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays. 1477-1489 - Hyuk Ryu, Eun-Taek Sung, Sangyong Park, Je-Kwang Cho
Fast Automatic Frequency Calibrator Using an Adaptive Frequency Search Algorithm. 1490-1496 - Shraddha Bodhe
Reordering Tests for Efficient Fail Data Collection and Tester Time Reduction. 1497-1505 - Yu Liu, Yier Jin
Silicon Demonstration of Hardware Trojan Design and Detection in Wireless Cryptographic ICs. 1506-1519 - Jiliang Zhang
Publicly Verifiable Watermarking for Intellectual Property Protection in FPGA Design. 1520-1527 - Anita Aghaie, Mehran Mozaffari Kermani
Fault Diagnosis Schemes for Low-Energy Block Cipher Midori Benchmarked on FPGA. 1528-1536 - Dwaipayan Biswas
Low-Complexity Framework for Movement Classification Using Body-Worn Sensors. 1537-1548 - Sumeet S. Kumar
Fighting Dark Silicon: Toward Realizing Efficient Thermal-Aware 3-D Stacked Multiprocessors. 1549-1562 - Mohammad Ali Montazerolghaem, Tohid Moosazadeh, Mohammad Yavari
A Single Channel Split ADC Structure for Digital Background Calibration in Pipelined ADCs. 1563-1567 - Bhagyaraja Adapa, Dwaipayan Biswas
Coordinate Rotation-Based Low Complexity K-Means Clustering Architecture. 1568-1572 - Yeongkyo Seo
Fast and Disturb-Free Nonvolatile Flip-Flop Using Complementary Polarizer MTJ. 1573-1577 - Hayate Okuhara
Power Optimization Methodology for Ultralow Power Microcontroller With Silicon on Thin BOX MOSFET. 1578-1582 - Ali Ahmed
Resource-Efficient SRAM-Based Ternary Content Addressable Memory. 1583-1587 - Hyeonggyu Kim
Write-Amount-Aware Management Policies for STT-RAM Caches. 1588-1592
Volume 25, Number 5, May 2017
- Jing Guo
Novel Radiation-Hardened-by-Design (RHBD) 12T Memory Cell for Aerospace Applications in Nanoscale CMOS Technology. 1593-1600 - Xiaole Cui, Xiaoxin Cui
An Enhancement of Crosstalk Avoidance Code Based on Fibonacci Numeral System for Through Silicon Vias. 1601-1610 - Manqing Mao
A Multilayer Approach to Designing Energy-Efficient and Reliable ReRAM Cross-Point Array System. 1611-1621 - Soon-Chan Kwon
A Fast and Reliable Cross-Point Three-State/Cell ReRAM. 1622-1631 - Parham Hosseinzadeh Namin, Roberto Muscedere, Majid Ahmadi
Digit-Level Serial-In Parallel-Out Multiplier Using Redundant Representation for a Class of Finite Fields. 1632-1643 - M. Hassan Najafi
Time-Encoded Values for Highly Efficient Stochastic Circuits. 1644-1657 - Serdar Süer Erdem, Tugrul Yanik, Anil Çelebi
A General Digit-Serial Architecture for Montgomery Modular Multiplication. 1658-1668 - Trong Huynh Bao, Julien Ryckaert, Zsolt Tokei
Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond. 1669-1680 - Tao-Tao Zhu
Error-Resilient Integrated Clock Gate for Clock-Tree Power Optimization on a Wide Voltage IOT Processor. 1681-1693 - Jeremy Schlachter
Design and Applications of Approximate Circuits by Gate-Level Pruning. 1694-1702 - Yu-Min Lee
NaPer: A TSV Noise-Aware Placer. 1703-1713 - Cang Liu
Hardware Architecture Based on Parallel Tiled QRD Algorithm for Future MIMO Systems. 1714-1724 - Cheng-Ta Chiang
Design of a CMOS Chlorophyll Concentration Detector Based on Organic Chlorophyll Battery for Measuring Vegetable Chlorophyll Concentration. 1725-1730 - SangYun Kim
An Inductive 2-D Position Detection IC With 99.8% Accuracy for Automotive EMR Gear Control System. 1731-1741 - Je-Kwang Cho
A 6-mW, 70.1-dB SNDR, and 20-MHz BW Continuous-Time Sigma-Delta Modulator Using Low-Noise High-Linearity Feedback DAC. 1742-1755 - Mohammad Taherzadeh-Sani
A 170-dB Ω CMOS TIA With 52-pA Input-Referred Noise and 1-MHz Bandwidth for Very Low Current Sensing. 1756-1766 - Yiping Zhang
28-nm Latch-Type Sense Amplifier Modification for Coupling Suppression. 1767-1773 - Ravi Shankar R. Velampati, El-Sayed A. M. Hasaneen
Floating Gate Nonvolatile Memory Using Individually Cladded Monodispersed Quantum Dots. 1774-1781 - Suganthi Venkatachalam, Seok-Bum Ko
Design of Power and Area Efficient Approximate Multipliers. 1782-1786 - Huyen Thi Pham, Hanho Lee
Two-Extra-Column Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes. 1787-1791 - HoonSeok Kim
Corrections to "Crosstalk-Canceling Multimode Interconnect Using Transmitter Encoding". 1792
Volume 25, Number 6, June 2017
- Jinho Lee
Excavating the Hidden Parallelism Inside DRAM Architectures With Buffered Compares. 1793-1806 - Xiuyuan Bi
Cross-Layer Optimization for Multilevel Cell STT-RAM Caches. 1807-1820 - JaeHyun Seo, Sangheon Lee, Kwangmin Kim, Sooeun Lee, Hyunsang Hwang, Byungsub Kim
Automatic ReRAM SPICE Model Generation From Empirical Data for Fast ReRAM-Circuit Coevaluation. 1821-1830 - Muhammad Sanaullah
Analytical Models of High-Speed RLC Interconnect Delay for Complex and Real Poles. 1831-1841 - Khaled E. Ahmed
Overloaded CDMA Crossbar for Network-On-Chip. 1842-1855 - Sung Joo Park
Application of Machine Learning for Optimization of 3-D Integrated Circuits and Systems. 1856-1865 - Pouya Taatizadeh
Emulation Infrastructure for the Evaluation of Hardware Assertions for Post-Silicon Validation. 1866-1880 - Sandeep Chandran
Managing Trace Summaries to Minimize Stalls During Postsilicon Validation. 1881-1894 - Yue Ma
Improving System-Level Lifetime Reliability of Multicore Soft Real-Time Systems. 1895-1905 - Ze-ke Wang
Multikernel Data Partitioning With Channel on OpenCL-Based FPGAs. 1906-1918 - Kaifeng Xia
A Memory-Based FFT Processor Design With Generalized Efficient Conflict-Free Address Schemes. 1919-1929 - Saleh Abdel-Hafeez, Ann Gordon-Ross
An Efficient O(N) Comparison-Free Sorting Algorithm. 1930-1942 - Yongyuan Li, Zhangming Zhu
A 30-W 90% Efficiency Dual-Mode Controlled DC-DC Controller With Power Over Ethernet Interface for Power Device. 1943-1953 - Xiang Zhang
An 80.4% Peak Power Efficiency Adaptive Supply Class H Power Amplifier for Audio Applications. 1954-1965 - Andrew P. Nicholson
A Statistical Design Approach Using Fixed and Variable Width Transconductors for Positive-Feedback Gain-Enhancement OTAs. 1966-1977 - Aibin Yan
Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology. 1978-1982 - Karama M. AL-Tamimi
Preweighted Linearized VCO Analog-to-Digital Converter. 1983-1987 - Irith Pomeranz
Selecting Replacements for Undetectable Path Delay Faults. 1988-1992
Volume 25, Number 7, July 2017
- Sheng Wang
A Variation-Tolerant Near-Threshold Processor With Instruction-Level Error Correction. 1993-2006 - Hiroshi Fuketa
A Closed-Form Expression for Minimum Operating Voltage of CMOS D Flip-Flop. 2007-2016 - Saman Kiamehr
Temperature-Aware Dynamic Voltage Scaling to Improve Energy Efficiency of Near-Threshold Computing. 2017-2026 - Hochul Lee
A Word Line Pulse Circuit Technique for Reliable Magnetoelectric Random Access Memory. 2027-2034 - Prabal Basu, Rajesh Jayashankara Shridevi, Koushik Chakraborty
IcoNoClast: Tackling Voltage Noise in the NoC Power Supply Through Flow-Control and Routing Algorithms. 2035-2044 - Dae-Hyun Kim
An ECC-Assisted Postpackage Repair Methodology in Main Memory Systems. 2045-2058 - Fatemeh Refan, Bijan Alizadeh
Bridging Presilicon and Postsilicon Debugging by Instruction-Based Trace Signal Selection in Modern Processors. 2059-2070 - Raviteja P. Reddy, Amit Acharyya
A Cost-Effective Fault Tolerance Technique for Functional TSV in 3-D ICs. 2071-2080 - Marta Ortín-Obón
Contrasting Laser Power Requirements of Wavelength-Routed Optical NoC Topologies Subject to the Floorplanning, Placement, and Routing Constraints of a 3-D-Stacked System. 2081-2094 - Chenchen Fu
Maximizing Common Idle Time on Multicore Processors With Shared Memory. 2095-2108 - Moongon Jung
Design Methodologies for Low-Power 3-D ICs With Advanced Tier Partitioning. 2109-2117 - Kyungwook Chang
Impact and Design Guideline of Monolithic 3-D IC at the 7-nm Technology Node. 2118-2129 - Nuno Neves
Adaptive In-Cache Streaming for Efficient Data Management. 2130-2143 - Dina M. Ellaithy
Double Logarithmic Arithmetic Technique for Low-Power 3-D Graphics Applications. 2144-2152 - Zhe Yuan, Yongpan Liu
CP-FPGA: Energy-Efficient Nonvolatile FPGA With Offline/Online Checkpointing Optimization. 2153-2163 - Hesheng Lin, Wing Chun Chan, Wai Kwong Lee, Zhirong Chen, Mansun Chan, Min Zhang
High-Current Drivability Fibonacci Charge Pump With Connect-Point-Shift Enhancement. 2164-2173 - Sami Ur Rehman
A Temperature Estimation Method Using the Ratio of Emitter-to-Base Voltages. 2174-2182 - Weize Yu
Security-Adaptive Voltage Conversion as a Lightweight Countermeasure Against LPA Attacks. 2183-2187 - Ahmad A. Hiasat
A Residue-to-Binary Converter for the Extended Four-Moduli Set {2n-1, 2n+1, 22n+1, 22n+p}. 2188-2192
Volume 25, Number 8, August 2017
- Chenyuan Zhao, Yang Yi
Interspike-Interval-Based Analog Spike-Time-Dependent Encoder for Neuromorphic Processors. 2193-2205 - Hoang Anh Du Nguyen
On the Implementation of Computation-in-Memory Parallel Adder. 2206-2219 - Fengbin Tu
Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns. 2220-2233 - Pang-Yen Chou
Matched-Routing Common-Centroid 3-D MOM Capacitors for Low-Power Data Converters. 2234-2247 - Abinash Mohanty
RTN in Scaled Transistors for On-Chip Random Seed Generation. 2248-2257 - Neel Gala
Approximate Error Detection With Stochastic Checkers. 2258-2270 - Soonyoung Cha, Taizhi Liu, Linda Milor
Negative Bias Temperature Instability and Gate Oxide Breakdown Modeling in Circuits With Die-to-Die Calibration Through Power Supply and Ground Signal Measurements. 2271-2284 - Chaudhry Adnan Aslam
Mitigating Stuck Cell Failures in MLC NAND Flash Memory via Inferred Erasure Decoding. 2285-2295 - Reda Boumchedda
High-Density 4T SRAM Bitcell in 14-nm 3-D CoolCube Technology Exploiting Assist Techniques. 2296-2306 - Safeen Huda
Leveraging Unused Resources for Energy Optimization of FPGA Interconnect. 2307-2320 - Peng Cao
Context Management Scheme Optimization of Coarse-Grained Reconfigurable Architecture for Multimedia Applications. 2321-2331 - Claudia Patricia Renteria-Mejia, Jaime Velasco-Medina
High-Throughput Ring-LWE Cryptoprocessors. 2332-2345 - Ching-Wen Lin
A Processor and Cache Online Self-Testing Methodology for OS-Managed Platform. 2346-2359 - ChaiYong Lim
A 50-mA 99.2% Peak Current Efficiency, 250-ns Settling Time Digital Low-Dropout Regulator With Transient Enhanced PI Controller. 2360-2370 - Liang Wu
A 0.9-5.8-GHz Software-Defined Receiver RF Front-End With Transformer-Based Current-Gain Boosting and Harmonic Rejection Calibration. 2371-2382 - Ngoc Le Ba
Design of Temperature-Aware Low-Voltage 8T SRAM in SOI Technology for High-Temperature Operation (25 %C-300 %C). 2383-2387 - Telajala Venkata Mahendra
Self-Controlled High-Performance Precharge-Free Content-Addressable Memory. 2388-2392
Volume 25, Number 9, September 2017
- Krishnendu Chakrabarty
Editorial. 2393 - Ramtin Zand
Energy-Efficient and Process-Variation-Resilient Write Circuit Schemes for Spin Hall Effect MRAM Device. 2394-2401 - Yelim Youn, Kwangmin Kim, Jae-Yoon Sim
Investigation on the Worst Read Scenario of a ReRAM Crossbar Array. 2402-2410 - Amit Kazimirsky, Adam Teman
A 0.65-V, 500-MHz Integrated Dynamic and Static RAM for Error Tolerant Applications. 2411-2418 - Mingyu Wang
A Spatial and Temporal Locality-Aware Adaptive Cache Design With Network Optimization for Tiled Many-Core Architectures. 2419-2433 - Tong-Yu Hsieh
Cost-Effective Enhancement on Both Yield and Reliability for Cache Designs Based on Performance Degradation Tolerance. 2434-2448 - Randy W. Mann
Array Termination Impacts in Advanced SRAM. 2449-2457 - Ryan Gary Kim
Imitation Learning for Dynamic VFI Control in Large-Scale Manycore Systems. 2458-2471 - Chen Hou
Stopping-Time Management of Smart Sensing Nodes Based on Tradeoffs Between Accuracy and Power Consumption. 2472-2485 - Carl Ingemarsson
Efficient FPGA Mapping of Pipeline SDF FFT Cores. 2486-2497 - Dawei Li, Siddhartha Joshi, Ji-Hoon Kim, Seda Ogrenci Memik
End-to-End Analysis of Integration for Thermocouple-Based Sensors Into 3-D ICs. 2498-2511 - Palkesh Jain
Fast Stochastic Analysis of Electromigration in Power Distribution Networks. 2512-2524 - Weina Lu
Going Cooler With Timing-Constrained TeSHoP: A Temperature Sensing-Based Hotspot-Driven Placement Technique for FPGAs. 2525-2537 - Divya Pathak
Smart Grid on Chip: Work Load-Balanced On-Chip Power Delivery. 2538-2551 - Shuai Chen
All-Digital Calibration of Timing Mismatch Error in Time-Interleaved Analog-to-Digital Converters. 2552-2560 - Taeyoung Kim
Energy and Lifetime Optimizations for Dark Silicon Manycore Microprocessor Considering Both Hard and Soft Errors. 2561-2574 - Nijwm Wary
Current-Mode Triline Transceiver for Coded Differential Signaling Across On-Chip Global Interconnects. 2575-2587 - Subrahmanyam Mula
Algorithm and Architecture Design of Adaptive Filters With Error Nonlinearities. 2588-2601 - Miao Tony He
Test-Point Insertion Efficiency Analysis for LBIST in High-Assurance Applications. 2602-2615 - Xiaoliang Dai
Using a Device State Library to Boost the Performance of TCAD Mixed-Mode Simulation. 2616-2624 - Na Gong
SPIDER: Sizing-Priority-Based Application-Driven Memory for Mobile Video Applications. 2625-2634 - Chun-Hsing Li
A 7.1-mW K/Ka-Band Mixer With Configurable Bondwire Resonators in 65-nm CMOS. 2635-2648 - Sihwan Kim
Calibration of Floating-Gate SoC FPAA System. 2649-2657 - Xiang Feng
Design of an Area-Effcient Million-Bit Integer Multiplier Using Double Modulus NTT. 2658-2662 - Vicente Torres
A Fast and Low-Complexity Operator for the Computation of the Arctangent of a Complex Number. 2663-2667 - Sheis Abolma'ali, Nika Mansouri-Ghiasi, Mehdi Kamal, Ali Afzali-Kusha
Efficient Critical Path Identification Based on Viability Analysis Method Considering Process Variations. 2668-2672 - Priyadarshini Panda
Energy-Efficient Object Detection Using Semantic Decomposition. 2673-2677 - Qiaosha Zou
Thermomechanical Stress-Aware Management for 3-D IC Designs. 2678-2682
Volume 25, Number 10, October 2017
- Farshad Firouzi, Bahar J. Farahani
Guest Editorial: Alternative Computing and Machine Learning for Internet of Things. 2685-2687 - Arash Ardakani
VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing. 2688-2699 - Michael Gautschi
Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices. 2700-2713 - Jinsu Lee
A 17.5-fJ/bit Energy-Efficient Analog SRAM for Mixed-Signal Processing. 2714-2723 - Naoya Onizawa
Area/Energy-Efficient Gammatone Filters Based on Stochastic Computation. 2724-2735 - Ying Wang
Resilience-Aware Frequency Tuning for Neural-Network-Based Approximate Computing Chips. 2736-2748 - Anil Kanduri
Accuracy-Aware Power Management for Many-Core Systems Running Error-Resilient Applications. 2749-2762 - Zhisheng Wang
Accelerating Recurrent Neural Networks: A Memory-Efficient Approach. 2763-2775 - Bo-Cheng Charles Lai
An Efficient Hierarchical Banking Structure for Algorithmic Multiported Memory on FPGA. 2776-2788 - Luechao Yuan
A Flexible Divide-and-Conquer MPSoC Architecture for MIMO Interference Cancellation. 2789-2802 - Huai-Ting Li, Ching-Yao Chou, Yuan-Ting Hsieh, Wei-Ching Chu, An-Yeu Wu
Variation-Aware Reliable Many-Core System Design by Exploiting Inherent Core Redundancy. 2803-2816 - Qiliang Shao, Zhenji Hu, Shaobo Chen, Pingxiuqi Chen, Jiafeng Xie
Low-Complexity Digit-Level Systolic Gaussian Normal Basis Multiplier. 2817-2827 - Aurangozeb
Time-Domain Arithmetic Logic Unit With Built-In Interconnect. 2828-2841 - Jian Yan
Lossless Compression Decoders for Bitstreams and Software Binaries Based on High-Level Synthesis. 2842-2855 - Lennart Bamberg
High-Level Energy Estimation for Submicrometric TSV Arrays. 2856-2866 - Jongsok Choi
From Pthreads to Multicore Hardware Systems in LegUp High-Level Synthesis for FPGAs. 2867-2880 - Shengcheng Wang
Electromigration-Aware Local-Via Allocation in Power/Ground TSVs of 3-D ICs. 2881-2892 - Jinn-Shyan Wang, Shih-Nung Wei
Process/Voltage/Temperature-Variation-Aware Design and Comparative Study of Transition-Detector-Based Error-Detecting Latches for Timing-Error-Resilient Pipelined Systems. 2893-2906 - Shunbin Li
An Adaptive PAM-4 Analog Equalizer With Boosting-State Detection in the Time Domain. 2907-2916 - Hansraj Bhamra
A Noise-Power-Area Optimized Biosensing Front End for Wireless Body Sensor Nodes and Medical Implantable Devices. 2917-2928 - Sang Min Lee
A DAC With an Impedance Attenuator and Distortion Analysis Using Volterra Series. 2929-2938 - Jiaji He
Hardware Trojan Detection Through Chip-Free Electromagnetic Side-Channel Statistical Analysis. 2939-2948 - Cesar Acero, Derek Feltham, Yingdi Liu, Elham K. Moghaddam, Nilanjan Mukherjee, Marek Patyra, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer
Embedded Deterministic Test Points. 2949-2961 - Xiaoyu Sun
Low-VDD Operation of SRAM Synaptic Array for Implementing Ternary Neural Network. 2962-2965 - Antonio J. Ginés
Fast Background Calibration of Sampling Timing Skew in SHA-Less Pipeline ADCs. 2966-2970 - Christopher Fritz
Fast Binary Counters Based on Symmetric Stacking. 2971-2975 - Yangxurui Liu
Architecture Design of a Memory Subsystem for Massive MIMO Baseband Processing. 2976-2980
Volume 25, Number 11, November 2017
- Tongda Wu
DVFS-Based Long-Term Task Scheduling for Dual-Channel Solar-Powered Sensor Nodes. 2981-2994 - Zhekai Xiao
A Hysteretic Switched-Capacitor DC-DC Converter With Optimal Output Ripple and Fast Transient Response. 2995-3005 - Younghyun Lim
An External Capacitor-Less Ultralow-Dropout Regulator Using a Loop-Gain Stabilizing Technique for High Power-Supply Rejection Over a Wide Range of Load Current. 3006-3018 - Longfei Wang
Efficiency, Stability, and Reliability Implications of Unbalanced Current Sharing Among Distributed On-Chip Voltage Regulators. 3019-3032 - Jin-Fa Lin
Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes. 3033-3044 - Kristof Blutman, Hamed Fatemi, Ajay Kapoor, Andrew B. Kahng, Jiajia Li
Logic Design Partitioning for Stacked Power Domains. 3045-3056 - Sumantra Sarkar
Adaptive Bus Encoding for Transition Reduction on Off-Chip Buses With Dynamically Varying Switching Characteristics. 3057-3066 - Fabrizio Cairo, Marco Vacca, Giovanna Turvani
Domain Wall Interconnections for NML. 3067-3076 - Siyuan Xu
Exposing Approximate Computing Optimizations at Different Levels: From Behavioral to Gate-Level. 3077-3088 - K. M. Mohsin, Ashok Srivastava
Modeling of Joule Heating Induced Effects in Multiwall Carbon Nanotube Interconnects. 3089-3098 - Khanh N. Dang
A Comprehensive Reliability Assessment of Fault-Resilient Network-on-Chip Using Analytical Model. 3099-3112 - Xinwang Zhang, Zipeng Chen, Yanqiang Gao, Feng Ma, Jiachen Hao, Guodong Zhu, Baoyong Chi
An Interference-Robust Reconfigurable Receiver With Automatic Frequency-Calibrated LNA in 65-nm CMOS. 3113-3124 - Amr M. S. Tosson
A Study of the Effect of RRAM Reliability Soft Errors on the Performance of RRAM-Based Neuromorphic Systems. 3125-3137 - Maryam Karimi
A Low Area Overhead NBTI/PBTI Sensor for SRAM Memories. 3138-3151 - Guangda Zhang
Handling Physical-Layer Deadlock Caused by Permanent Faults in Quasi-Delay-Insensitive Networks-on-Chip. 3152-3165 - Tzung-Je Lee, Tsung-Yi Tsai, Wei Lin, U-Fat Chio, Chua-Chin Wang
A Dynamic Leakage and Slew Rate Compensation Circuit for 40-nm CMOS Mixed-Voltage Output Buffer. 3166-3174 - Vineeth Sarma, Chithira Ravi, Bibhudatta Sahoo
Achieving Theoretical Limit of SFDR in Pipelined ADCs. 3175-3185 - José María Algueta-Miguel, Jaime Ramírez-Angulo
A Simple Miller Compensation With Essential Bandwidth Improvement. 3186-3192 - Seyed Alireza Zahrai, Marina Zlochisti, Nicolas Le Dortz, Marvin Onabajo
A Low-Power High-Speed Hybrid ADC With Merged Sample-and-Hold and DAC Functions for Efficient Subranging Time-Interleaved Operation. 3193-3206 - Hao-Ting Shen
Poly-Si-Based Physical Unclonable Functions. 3207-3217 - Wen Yuan
A Switched-Capacitor-Controlled Digital-Current Modulated Class-E Transmitter. 3218-3226 - Shalini Pathak
LoCCo-Based Scan Chain Stitching for Low-Power DFT. 3227-3236 - Mehdi Sadi
Design of Reliable SoCs With BIST Hardware and Machine Learning. 3237-3250 - Hoseok Seol
In-DRAM Data Initialization. 3251-3254 - Suresh Mopuri
Low-Complexity Methodology for Complex Square-Root Computation. 3255-3259 - Boyu Hu
An R2R-DAC-Based Architecture for Equalization-Equipped Voltage-Mode PAM-4 Wireline Transmitter Design. 3260-3264
Volume 25, Number 12, December 2017
- Anirban Sengupta
Guest Editorial Securing IoT Hardware: Threat Models and Reliable, Low-Power Design Solutions. 3265-3267 - Leonid Azriel
Using Scan Side Channel to Detect IP Theft. 3268-3280 - Duy-Hieu Bui
AES Datapath Optimization Strategies for Low-Power Low-Energy Multisecurity-Level Internet-of-Things Applications. 3281-3290 - Thomas De Cnudde
Securing the PRESENT Block Cipher Against Combined Side-Channel Analysis and Fault Attacks. 3291-3301 - Hsiang-Jen Tsai
A Flexible Wildcard-Pattern Matching Accelerator via Simultaneous Discrete Finite Automata. 3302-3316 - Maxime Lecomte
An On-Chip Technique to Detect Hardware Trojans and Assist Counterfeit Identification. 3317-3330 - Yizhi Zhao
Chaotic Encrypted Polar Coding Scheme for General Wiretap Channel. 3331-3340 - Po-Hao Wang
ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures. 3341-3354 - Xiangyu Li
Energy-Efficient Side-Channel Attack Countermeasure With Awareness and Hybrid Configuration Based on It. 3355-3368 - Javad Gorji
A Process-Independent and Highly Linear DCO for Crowded Heterogeneous IoT Devices in 65-nm CMOS. 3369-3379 - Francisco Eugenio Potestad-Ordóñez
Vulnerability Analysis of Trivium FPGA Implementations. 3380-3389 - Xiaolong Guo, Raj Gautam Dutta, Prabhat Mishra
Automatic Code Converter Enhanced PCH Framework for SoC Trust Verification. 3390-3400 - José Miguel Mora-Gutierrez
Multiradix Trivium Implementations for Low-Power IoT Hardware. 3401-3405 - Jonathon Magaña, Daohang Shi, Jackson Melchert, Azadeh Davoodi
Are Proximity Attacks a Threat to the Security of Split Manufacturing of Integrated Circuits? 3406-3419 - Fahim Rahman
Security Beyond CMOS: Fundamentals, Applications, and Roadmap. 3420-3433 - Yung-Hui Chung
An 11-bit 100-MS/s Subranged-SAR ADC in 65-nm CMOS. 3434-3443 - Qing Liu
A 400-MS/s 10-b 2-b/Step SAR ADC With 52-dB SNDR and 5.61-mW Power Dissipation in 65-nm CMOS. 3444-3454 - Gustavo Della Colletta
A 20-nW 0.25-V Inverter-Based Asynchronous Delta-Sigma Modulator in 130-nm Digital CMOS Process. 3455-3463 - Daniel Kraak
Impact and Mitigation of Sense Amplifier Aging Degradation Using Realistic Workloads. 3464-3472 - Shourya Gupta
A 32-nm Subthreshold 7T SRAM Bit Cell With Read Assist. 3473-3483 - Gyuseong Kang, Woong Choi, Jongsun Park
Embedded DRAM-Based Memory Customization for Low-Cost FFT Processor Design. 3484-3494 - Karthi Duraisamy, Partha Pratim Pande
Enabling High-Performance SMART NoC Architectures Using On-Chip Wireless Links. 3495-3508 - Giuseppe Scotti
Design of Low-Voltage High-Speed CML D-Latches in Nanometer CMOS Technologies. 3509-3520 - Sachin Kumar, Chip-Hong Chang
A Scaling-Assisted Signed Integer Comparator for the Balanced Five-Moduli Set RNS 2n-1, 2n, 2n+ 1, 2n+1-1, 2n-1-1. 3521-3533 - Zhenqiang Yong
An Energy-Efficient and Wide-Range Voltage Level Shifter With Dual Current Mirror. 3534-3538 - Haowen Luo
An Algorithm for Improving the Throughput of Serial Low-Complexity Chase Soft-Decision Reed-Solomon Decoder. 3539-3542 - Woo-Rham Bae
Use of Phase Delay Analysis for Evaluating Wideband Circuits: An Alternative to Group Delay Analysis. 3543-3547 - Xue Liu
Design and FPGA Implementation of a Reconfigurable Digital Down Converter for Wideband Applications. 3548-3552
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