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Jiang Hu
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2020 – today
- 2024
- [j110]Hengzhi Zhao, Jiwei Zhang, Jing Lu, Jiang Hu:
Approximate controllability and optimal control in fractional differential equations with multiple delay controls, fractional Brownian motion with Hurst parameter in 0H12, and Poisson jumps. Commun. Nonlinear Sci. Numer. Simul. 128: 107636 (2024) - [j109]Qianyong Wu, Jiang Hu:
Two-sample test of stochastic block models. Comput. Stat. Data Anal. 192: 107903 (2024) - [j108]Jiang Hu
, Xing Li:
A novel prediction model construction and result interpretation method for slope deformation of deep excavated expansive soil canals. Expert Syst. Appl. 236: 121326 (2024) - [j107]Jiang Hu
A multilevel optimization approach for daily scheduling of combined heat and power units with integrated electrical and thermal storage. Expert Syst. Appl. 250: 123729 (2024) - [j106]Jiang Hu
NextPolish2: A Repeat-aware Polishing Tool for Genomes Assembled Using HiFi Long Reads. Genom. Proteom. Bioinform. 22(1) (2024) - [j105]Yang Yu, Zhekai Du, Lichao Meng, Jingjing Li
Adaptive online continual multi-view learning. Inf. Fusion 103: 102020 (2024) - [j104]Jianghao Li
The limiting spectral distribution of large random permutation matrices. J. Appl. Probab. 61(4): 1301-1318 (2024) - [j103]Jiang Hu, Kangkang Deng, Jiayuan Wu, Quanzheng Li:
A projected semismooth Newton method for a class of nonconvex composite programs with strong prox-regularity. J. Mach. Learn. Res. 25: 56:1-56:32 (2024) - [j102]Cheng Chen
MA-SAM: Modality-agnostic SAM adaptation for 3D medical image segmentation. Medical Image Anal. 98: 103310 (2024) - [j101]Lu Yan, Jiang Hu, Lixiu Wu:
Distributed hypothesis testing for large dimensional two-sample mean vectors. Stat. Comput. 34(6): 187 (2024) - [j100]Jiang Hu
Riemannian Natural Gradient Methods. SIAM J. Sci. Comput. 46(1): 204- (2024) - [j99]Chen-Chia Chang
Toward Fully Automated Machine Learning for Routability Estimator Development. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(3): 970-982 (2024) - [j98]Yishuang Lin
MMM: Machine Learning-Based Macro-Modeling for Linear Analog ICs and ADC/DACs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(12): 4740-4752 (2024) - [j97]Jiayuan Wu
Convergence Analysis of an Adaptively Regularized Natural Gradient Method. IEEE Trans. Signal Process. 72: 2527-2542 (2024) - [c212]Jianfeng Song, Rongjian Liang, Yu Gong, Bo Yuan, Jiang Hu:
DiMO-Sparse: Differentiable Modeling and Optimization of Sparse CNN Dataflow and Hardware Architecture. DATE 2024: 1-6 - [c211]Jiaojiao Zhang, Jiang Hu, Mikael Johansson:
Composite Federated Learning with Heterogeneous Data. ICASSP 2024: 8946-8950 - [c210]Jinxin Wang, Jiang Hu, Shixiang Chen, Zengde Deng, Anthony Man-Cho So:
Decentralized Non-Smooth Optimization Over the Stiefel Manifold. SAM 2024: 1-5 - [c209]Erick Carvajal Barboza, Mahesh Ketkar, Paul Gratz, Jiang Hu:
Aiding Microprocessor Performance Validation with Machine Learning. ISPASS 2024: 1-9 - [c208]Jiachi Chen
Identifying Smart Contract Security Issues in Code Snippets from Stack Overflow. ISSTA 2024: 1198-1210 - [c207]Cristhian Roman-Vicharra
Flip-Flop Centric Incremental Placement for Simultaneous Timing and Clock Network Power Optimization. MLCAD 2024: 11:1-11:7 - [c206]Prianka Sengupta
MinBLoG: Minimization of Boolean Logic Functions using Graph Attention Network. MLCAD 2024: 24:1-24:8 - [e3]Hussam Amrouch, Jiang Hu, Siddharth Garg, Yibo Lin:
Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, MLCAD 2024, Salt Lake City, UT, USA, September 9-11, 2024. ACM 2024, ISBN 979-8-4007-0699-8 [contents] - [i23]Jiang Hu, Quanzheng Li:
AdaFish: Fast low-rank parameter-efficient fine-tuning by using second-order information. CoRR abs/2403.13128 (2024) - [i22]Jiaojiao Zhang, Jiang Hu, Anthony Man-Cho So, Mikael Johansson:
Nonconvex Federated Learning on Compact Smooth Submanifolds With Heterogeneous Data. CoRR abs/2406.08465 (2024) - [i21]Jiachi Chen, Chong Chen, Jiang Hu, John Grundy, Yanlin Wang, Ting Chen, Zibin Zheng:
Identifying Smart Contract Security Issues in Code Snippets from Stack Overflow. CoRR abs/2407.13271 (2024) - [i20]Guanglei Zhou, Bhargav Korrapati, Gaurav Rajavendra Reddy, Jiang Hu, Yiran Chen, Dipto G. Thakurta:
PatternPaint: Generating Layout Patterns Using Generative AI and Inpainting Techniques. CoRR abs/2409.01348 (2024) - 2023
- [j96]Gregory Tai Xiang Ang
Exact and approximate computation of critical values of the largest root test in high dimension. Commun. Stat. Simul. Comput. 52(5): 2177-2193 (2023) - [j95]Xing Li
A spatiotemporal identification method for deformation characteristics of expansive soil canal slope based on spectral clustering. Expert Syst. Appl. 225: 120108 (2023) - [j94]Yukun He
T2T-YAO: A Telomere-to-Telomere Assembled Diploid Reference Genome for Han Chinese. Genom. Proteom. Bioinform. 21(6): 1085-1100 (2023) - [j93]Jiang Hu
Examining the impacts of fitness app features on user well-being. Inf. Manag. 60(5): 103796 (2023) - [j92]Zhiyao Xie
The Dark Side: Security and Reliability Concerns in Machine Learning for EDA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(4): 1171-1184 (2023) - [j91]Kishor Kunal
GNN-Based Hierarchical Annotation for Analog Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(9): 2801-2814 (2023) - [j90]Yaguang Li
Performance-driven Wire Sizing for Analog Integrated Circuits. ACM Trans. Design Autom. Electr. Syst. 28(2): 19:1-19:23 (2023) - [c205]Chen-Chia Chang, Jingyu Pan, Zhiyao Xie, Yaguang Li, Yishuang Lin, Jiang Hu, Yiran Chen:
Fully Automated Machine Learning Model Development for Analog Placement Quality Prediction. ASP-DAC 2023: 58-63 - [c204]Chen-Chia Chang, Jingyu Pan, Zhiyao Xie, Jiang Hu, Yiran Chen:
Rethink before Releasing Your Model: ML Model Extraction Attack in EDA. ASP-DAC 2023: 252-257 - [c203]Rongjian Liang
BufFormer: A Generative ML Framework for Scalable Buffering. ASP-DAC 2023: 264-270 - [c202]Jiang Hu, Yang Zhao, Erying Yi:
Application of Engineering Cost Database to Modern Power Plant Management. BMSB 2023: 1-4 - [c201]Erika S. Alcorta, Andreas Gerstlauer, Chenhui Deng, Qi Sun, Zhiru Zhang, Ceyu Xu, Lisa Wu Wills, Daniela Sanchez Lopera, Wolfgang Ecker, Siddharth Garg, Jiang Hu:
Special Session: Machine Learning for Embedded System Design. CODES+ISSS 2023: 28-37 - [c200]Jiang Hu:
Lightning Talk: Power and Performance Reconciliation - from Tradeoff to Win-Win. DAC 2023: 1-2 - [c199]Jiang Hu, Jie Zhang, Huigang Liang:
Privacy Policy and Hosts' Concerns on Accommodation Sharing Platforms. HICSS 2023: 6399-6408 - [c198]Hailiang Hu, Donghao Fang, Wuxi Li, Bo Yuan, Jiang Hu:
Systolic Array Placement on FPGAs. ICCAD 2023: 1-9 - [c197]Jiang Hu, Andrew B. Kahng:
Invited Paper: The Inevitability of AI Infusion Into Design Closure and Signoff. ICCAD 2023: 1-7 - [c196]Kunal Bharathi, Sunil P. Khatri, Jiang Hu:
Scaled Population Division for Approximate Computing. ISLPED 2023: 1-6 - [c195]Chunkai Fu, Ben Trombley, Hua Xiang, Gi-Joon Nam, Jiang Hu:
Machine Learning Techniques for Pre-CTS Identification of Timing Critical Flip-Flops. ISVLSI 2023: 1-6 - [c194]Yishuang Lin, Yaguang Li, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu:
MMM: Machine Learning-Based Macro-Modeling for Linear Analog ICs and ADC/DACs. MLCAD 2023: 1-6 - [c193]Prianka Sengupta, Aakash Tyagi, Yiran Chen, Jiang Hu:
Early Identification of Timing Critical RTL Components using ML based Path Delay Prediction. MLCAD 2023: 1-6 - [i19]Jiang Hu, Kangkang Deng, Na Li, Quanzheng Li:
Decentralized Riemannian natural gradient methods with Kronecker-product approximations. CoRR abs/2303.09611 (2023) - [i18]Erick Carvajal Barboza, Mahesh Ketkar, Michael Kishinevsky, Paul Gratz, Jiang Hu:
Machine Learning for Microprocessor Performance Bug Localization. CoRR abs/2303.15280 (2023) - [i17]Jinxin Wang, Jiang Hu, Shixiang Chen, Zengde Deng, Anthony Man-Cho So:
Decentralized Weakly Convex Optimization Over the Stiefel Manifold. CoRR abs/2303.17779 (2023) - [i16]Jiang Hu, Jiaojiao Zhang, Kangkang Deng:
Achieving Consensus over Compact Submanifolds. CoRR abs/2306.04769 (2023) - [i15]Nithyashankari Gummidipoondi Jayasankaran, Hao Guo, Satwik Patnaik, Jeyavijayan Rajendran, Jiang Hu:
Securing Cloud FPGAs Against Power Side-Channel Attacks: A Case Study on Iterative AES. CoRR abs/2307.02569 (2023) - [i14]Jiaojiao Zhang, Jiang Hu, Mikael Johansson:
Composite federated learning with heterogeneous data. CoRR abs/2309.01795 (2023) - [i13]Zhengliang Liu, Yiwei Li, Peng Shu, Aoxiao Zhong, Longtao Yang, Chao Ju, Zihao Wu, Chong Ma, Jie Luo, Cheng Chen, Sekeun Kim, Jiang Hu, Haixing Dai, Lin Zhao, Dajiang Zhu, Jun Liu, Wei Liu, Dinggang Shen, Tianming Liu, Quanzheng Li, Xiang Li:
Radiology-Llama2: Best-in-Class Large Language Model for Radiology. CoRR abs/2309.06419 (2023) - [i12]Cheng Chen, Juzheng Miao, Dufan Wu, Zhiling Yan, Sekeun Kim, Jiang Hu, Aoxiao Zhong, Zhengliang Liu, Lichao Sun, Xiang Li, Tianming Liu, Pheng-Ann Heng, Quanzheng Li:
MA-SAM: Modality-agnostic SAM Adaptation for 3D Medical Image Segmentation. CoRR abs/2309.08842 (2023) - 2022
- [j89]Jiang Hu, Xuetao Li:
Construction and Optimization of Green Supply Chain Management Mode of Agricultural Enterprises in the Digital Economy. Int. J. Inf. Syst. Supply Chain Manag. 15(2): 1-18 (2022) - [j88]Nguyen Hoang Nguyen, Duy Thien An Nguyen, Bingkun Ma, Jiang Hu:
The application of machine learning and deep learning in sport: predicting NBA players' performance and popularity. J. Inf. Telecommun. 6(2): 217-235 (2022) - [j87]Yangchun Zhang, Jiang Hu, Weiming Li:
CLT for linear spectral statistics of high-dimensional sample covariance matrices in elliptical distributions. J. Multivar. Anal. 191: 105007 (2022) - [j86]Jiang Hu, Xiaohui Kang, Fangfang Xu, Kezhi Huang, Bin Du, Li Weng:
Dynamic prediction of life-threatening events for patients in intensive care unit. BMC Medical Informatics Decis. Mak. 22(1): 276 (2022) - [j85]Rongjian Liang
Design Rule Violation Prediction at Sub-10-nm Process Nodes Using Customized Convolutional Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10): 3503-3514 (2022) - [j84]Zhiyao Xie
Preplacement Net Length and Timing Estimation by Customized Graph Neural Network. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4667-4680 (2022) - [j83]Nithyashankari Gummidipoondi Jayasankaran
Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction. IEEE Trans. Emerg. Top. Comput. 10(1): 386-403 (2022) - [j82]Lang Feng, Jiayi Huang
Toward Taming the Overhead Monster for Data-flow Integrity. ACM Trans. Design Autom. Electr. Syst. 27(3): 25:1-25:24 (2022) - [c192]Jiang Hu, Jie Zhang, Huigang Liang:
Examining the Role of Privacy Policy on Host Information Disclosure on Accommodation Sharing Platforms. AMCIS 2022 - [c191]Yishuang Lin, Rongjian Liang, Yaguang Li, Hailiang Hu, Jiang Hu:
Mapping Large Scale Finite Element Computing on to Wafer-Scale Engines. ASP-DAC 2022: 147-153 - [c190]Jingyu Pan, Chen-Chia Chang, Zhiyao Xie, Ang Li, Minxue Tang, Tunhou Zhang, Jiang Hu, Yiran Chen:
Towards collaborative intelligence: routability estimation based on decentralized private data. DAC 2022: 961-966 - [c189]Yishuang Lin, Yaguang Li, Donghao Fang, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu:
Are Analytical Techniques Worthwhile for Analog IC Placement? DATE 2022: 154-159 - [c188]Chan-Wei Hu, Jiang Hu, Sunil P. Khatri:
TD3lite: FPGA Acceleration of Reinforcement Learning with Structural and Representation Optimizations. FPL 2022: 79-85 - [c187]Rongjian Liang
A Stochastic Approach to Handle Non-Determinism in Deep Learning-Based Design Rule Violation Predictions. ICCAD 2022: 64:1-64:8 - [c186]Zhiyao Xie, Shiyu Li, Mingyuan Ma, Chen-Chia Chang, Jingyu Pan, Yiran Chen, Jiang Hu:
DEEP: Developing Extremely Efficient Runtime On-Chip Power Meters. ICCAD 2022: 76:1-76:9 - [c185]Rongjian Liang
Deep Learning Toolkit-Accelerated Analytical Co-Optimization of CNN Hardware and Dataflow. ICCAD 2022: 82:1-82:9 - [c184]Prianka Sengupta, Aakash Tyagi, Yiran Chen, Jiang Hu:
How Good Is Your Verilog RTL Code?: A Quick Answer from Machine Learning. ICCAD 2022: 89:1-89:9 - [c183]Jingyu Pan, Chen-Chia Chang, Zhiyao Xie, Jiang Hu, Yiran Chen:
Robustify ML-Based Lithography Hotspot Detectors. ICCAD 2022: 134:1-134:7 - [c182]Donghao Fang, Boyang Zhang, Hailiang Hu, Wuxi Li, Bo Yuan, Jiang Hu:
Global Placement Exploiting Soft 2D Regularity. ISPD 2022: 203-210 - [c181]Jianfeng Song, Dana Porter, Jiang Hu, Thomas H. Marek:
Double Deep Q-Learning Based Irrigation and Chemigation Control. ISQED 2022: 1-6 - [c180]Saumil Gogri, Aakash Tyagi, Michael Quinn, Jiang Hu:
Transaction Level Stimulus Optimization in Functional Verification Using Machine Learning Predictors. ISQED 2022: 71-76 - [c179]Hailiang Hu, Jiang Hu, Fan Zhang, Bing Tian, Ismail Bustany:
Machine-Learning Based Delay Prediction for FPGA Technology Mapping. SLIP 2022: 7:1-7:6 - [i11]Jingyu Pan, Chen-Chia Chang, Zhiyao Xie, Ang Li, Minxue Tang, Tunhou Zhang, Jiang Hu, Yiran Chen:
Towards Collaborative Intelligence: Routability Estimation based on Decentralized Private Data. CoRR abs/2203.16009 (2022) - [i10]Jiang Hu, Ruicheng Ao, Anthony Man-Cho So, Minghan Yang, Zaiwen Wen:
Riemannian Natural Gradient Methods. CoRR abs/2207.07287 (2022) - 2021
- [j81]Tonmoy Dhar, Kishor Kunal
ALIGN: A System for Automating Analog Layout. IEEE Des. Test 38(2): 8-18 (2021) - [j80]Shengfa Yang, Guanbing Xu, Li Wang, Wei Yang, Yi Xiao, Wenjie Li, Jiang Hu:
Field-derived relationships between fish habitat distribution and flow-sediment conditions in fluctuating backwater zone of the Three Gorges Reservoir. Ecol. Informatics 62: 101273 (2021) - [j79]Farhana Sharmin Snigdha
SeFAct2: Selective Feature Activation for Energy-Efficient CNNs Using Optimized Thresholds. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(7): 1423-1436 (2021) - [j78]Adriana C. Sanabria-Borbon
Analog/RF IP Protection: Attack Models, Defense Techniques, and Challenges. IEEE Trans. Circuits Syst. II Express Briefs 68(1): 36-41 (2021) - [j77]Lang Feng, Jeff Huang, Jiang Hu, Abhijith Reddy:
FastCFI: Real-time Control-Flow Integrity Using FPGA without Code Instrumentation. ACM Trans. Design Autom. Electr. Syst. 26(5): 39:1-39:39 (2021) - [c178]Tonmoy Dhar, Jitesh Poojary
Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models. ASP-DAC 2021: 158-163 - [c177]Zhiyao Xie, Rongjian Liang
Net2: A Graph Attention Network Method Customized for Pre-Placement Net Length Estimation. ASP-DAC 2021: 671-677 - [c176]Jiang Hu, Wei Li, Wenxia Liu, Xianggang He, Yu Zhang:
Research on Identification of Power Grid Weakness Based on Bayesian Inference. CECNet 2021: 159-170 - [c175]Meghna Madhusudan, Arvind K. Sharma, Yaguang Li, Jiang Hu, Sachin S. Sapatnekar, Ramesh Hajiani:
Analog Layout Generation using Optimized Primitives. DATE 2021: 1234-1239 - [c174]Erick Carvajal Barboza, Sara Jacob, Mahesh Ketkar, Michael Kishinevsky, Paul Gratz
Automatic Microprocessor Performance Bug Detection. HPCA 2021: 545-556 - [c173]Chen-Chia Chang, Jingyu Pan, Tunhou Zhang, Zhiyao Xie, Jiang Hu, Weiyi Qi, Chung-Wei Lin, Rongjian Liang
Automatic Routability Predictor Development Using Neural Architecture Search. ICCAD 2021: 1-9 - [c172]Rongjian Liang
FlowTuner: A Multi-Stage EDA Flow Tuner Exploiting Parameter Knowledge Transfer. ICCAD 2021: 1-9 - [c171]Juzheng Liu, Shiyu Su, Meghna Madhusudan, Mohsen Hassanpourghadi, Samuel Saunders, Qiaochu Zhang
From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning. ICCAD 2021: 1-9 - [c170]Tonmoy Dhar, Kishor Kunal
Machine Learning Techniques in Analog Layout Automation. ISPD 2021: 71-72 - [c169]Zhiyao Xie, Xiaoqing Xu, Matt Walker, Joshua Knebel, Kumaraguru Palaniswamy, Nicolas Hebert, Jiang Hu, Huanrui Yang, Yiran Chen
APOLLO: An Automated Power Modeling Framework for Runtime Power Introspection in High-Volume Commercial Microprocessors. MICRO 2021: 1-14 - [c168]Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu:
A Circuit Attention Network-Based Actor-Critic Learning Approach to Robust Analog Transistor Sizing. MLCAD 2021: 1-6 - [i9]Lang Feng, Jiayi Huang, Jeff Huang, Jiang Hu:
Toward Taming the Overhead Monster for Data-Flow Integrity. CoRR abs/2102.10031 (2021) - 2020
- [j76]Jiang Hu
NextPolish: a fast and efficient genome polishing tool for long-read assembly. Bioinform. 36(7): 2253-2255 (2020) - [j75]Miguel I. Aguirre-Urreta
Polynomial Regression and Measurement Error: Implications for Information Systems Research. Data Base 51(3): 55-80 (2020) - [j74]Cheng Zhuo
Noise-Aware DVFS for Efficient Transitions on Battery-Powered IoT Devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(7): 1498-1510 (2020) - [j73]Nithyashankari Gummidipoondi Jayasankaran
Breaking Analog Locking Techniques. IEEE Trans. Very Large Scale Integr. Syst. 28(10): 2157-2170 (2020) - [j72]Zhaoxi Fang
Three-User Cooperative NOMA Transmission. IEEE Wirel. Commun. Lett. 9(4): 465-469 (2020) - [c167]Jiang Hu, Wei He:
Examining the Impacts of Fitness App Functionalities. AMCIS 2020 - [c166]Zhiyao Xie, Haoxing Ren, Brucek Khailany, Ye Sheng, Santosh Santosh, Jiang Hu, Yiran Chen:
PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network. ASP-DAC 2020: 13-18 - [c165]Zhiyao Xie, Guan-Qi Fang, Yu-Hung Huang, Haoxing Ren, Yanqing Zhang, Brucek Khailany, Shao-Yun Fang, Jiang Hu, Yiran Chen, Erick Carvajal Barboza:
FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning. ASP-DAC 2020: 19-25 - [c164]Chaofei Yang, Hai Li, Yiran Chen, Jiang Hu:
Enhancing Generalization of Wafer Defect Detection by Data Discrepancy-aware Preprocessing and Contrast-varied Augmentation. ASP-DAC 2020: 145-150 - [c163]He Zhou, Sunil P. Khatri, Jiang Hu, Frank Liu:
Scaled Population Arithmetic for Efficient Stochastic Computing. ASP-DAC 2020: 611-616 - [c162]Kishor Kunal
GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits. DATE 2020: 55-60 - [c161]Jiang Hu, Wei He, Fred D. Davis:
When Hosts Disclose Their Private Information on Accommodation Sharing Platforms: An Information Commercialization Perspective. HICSS 2020: 1-9 - [c160]Zhiyao Xie, Hai Li, Xiaoqing Xu, Jiang Hu, Yiran Chen:
Fast IR Drop Estimation with Machine Learning : Invited Paper. ICCAD 2020: 13:1-13:8 - [c159]Tonmoy Dhar, Kishor Kunal
The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk). ICCAD 2020: 54:1-54:2 - [c158]Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu:
A Customized Graph Neural Network Model for Guiding Analog IC Placement. ICCAD 2020: 135:1-135:9 - [c157]Rongjian Liang
Routing-Free Crosstalk Prediction. ICCAD 2020: 163:1-163:9 - [c156]Nguyen Nguyen, Bingkun Ma, Jiang Hu:
Predicting National Basketball Association Players Performance and Popularity: A Data Mining Approach. ICCCI 2020: 293-304 - [c155]Kunal Bharathi, Jiang Hu, Sunil P. Khatri:
Scaled Population Subtraction for Approximate Computing. ICCD 2020: 348-355 - [c154]Hongxin Kong, Lang Feng, Chunhua Deng, Bo Yuan, Jiang Hu:
How Much Does Regularity Help FPGA Placement? FPT 2020: 76-84 - [c153]Kishor Kunal
Learning from Experience: Applying ML to Analog Circuit Design. ISPD 2020: 55 - [c152]Rongjian Liang
DRC Hotspot Prediction at Sub-10nm Process Nodes Using Customized Convolutional Network. ISPD 2020: 135-142 - [c151]Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu:
Exploring a Machine Learning Approach to Performance Driven Analog IC Placement. ISVLSI 2020: 24-29 - [c150]Adriana C. Sanabria-Borbon, Nithyashankari Gummidipoondi Jayasankaran, S. Y. Lee, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan (JV) Rajendran:
Schmitt Trigger-Based Key Provisioning for Locking Analog/RF Integrated Circuits. ITC 2020: 1-10 - [i8]Tonmoy Dhar, Kishor Kunal, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Parijat Mukherjee, Sachin S. Sapatnekar, Soner Yaldiz:
ALIGN: A System for Automating Analog Layout. CoRR abs/2008.10682 (2020) - [i7]Erick Carvajal Barboza, Sara Jacob, Mahesh Ketkar, Michael Kishinevsky, Paul Gratz, Jiang Hu:
Automatic Microprocessor Performance Bug Detection. CoRR abs/2011.08781 (2020) - [i6]Zhiyao Xie, Hai Li, Xiaoqing Xu, Jiang Hu, Yiran Chen:
Fast IR Drop Estimation with Machine Learning. CoRR abs/2011.13491 (2020) - [i5]Zhiyao Xie, Guan-Qi Fang, Yu-Hung Huang, Haoxing Ren, Yanqing Zhang, Brucek Khailany, Shao-Yun Fang, Jiang Hu, Yiran Chen, Erick Carvajal Barboza:
FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning. CoRR abs/2011.13493 (2020) - [i4]Zhiyao Xie, Haoxing Ren, Brucek Khailany, Ye Sheng, Santosh Santosh, Jiang Hu, Yiran Chen:
PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network. CoRR abs/2011.13494 (2020) - [i3]Zhiyao Xie, Rongjian Liang, Xiaoqing Xu, Jiang Hu, Yixiao Duan, Yiran Chen:
Net2: A Graph Attention Network Method Customized for Pre-Placement Net Length Estimation. CoRR abs/2011.13522 (2020) - [i2]Jingyu Pan, Chen-Chia Chang, Tunhou Zhang, Zhiyao Xie, Jiang Hu, Weiyi Qi, Chung-Wei Lin, Rongjian Liang, Joydeep Mitra, Elias Fallon, Yiran Chen:
Automatic Routability Predictor Development Using Neural Architecture Search. CoRR abs/2012.01737 (2020)
2010 – 2019
- 2019
- [j71]Miguel I. Aguirre-Urreta
Detecting Common Method Bias: Performance of the Harman's Single-Factor Test. Data Base 50(2): 45-70 (2019) - [j70]Qi Song, Yi Wang
Impact of the usage of social media in the workplace on team and employee performance. Inf. Manag. 56(8) (2019) - [j69]Jiang Hu, Bo Jiang, Lin Lin
Structured Quasi-Newton Methods for Optimization with Orthogonality Constraints. SIAM J. Sci. Comput. 41(4): A2239-A2269 (2019) - [j68]Deepashree Sengupta
An Analytical Approach for Error PMF Characterization in Approximate Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(1): 70-83 (2019) - [j67]Farhana Sharmin Snigdha
Dynamic Approximation of JPEG Hardware. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(2): 295-308 (2019) - [j66]Grace Li Zhang
EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration Under Process Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(4): 705-718 (2019) - [j65]Jiang Hu
Zoned safety monitoring model for uplift pressures of concrete dams. Trans. Inst. Meas. Control 41(14): 3952-3969 (2019) - [j64]Jiang Hu
Central Limit Theorem for Mutual Information of Large MIMO Systems With Elliptically Correlated Channels. IEEE Trans. Inf. Theory 65(11): 7168-7180 (2019) - [c149]Wenbin Xu, Lang Feng, Jeyavijayan Rajendran, Jiang Hu:
Layout recognition attacks on split manufacturing. ASP-DAC 2019: 45-50 - [c148]Farhana Sharmin Snigdha, Ibrahim Ahmed, Susmita Dey Manasi, Meghna G. Mankalale, Jiang Hu, Sachin S. Sapatnekar:
SeFAct: selective feature activation and early classification for CNNs. ASP-DAC 2019: 487-492 - [c147]He Zhou, Sunil P. Khatri, Jiang Hu, Frank Liu:
A Memory-Efficient Markov Decision Process Computation Framework Using BDD-based Sampling Representation. DAC 2019: 12 - [c146]Kishor Kunal
ALIGN: Open-Source Analog Layout Automation from the Ground Up. DAC 2019: 77 - [c145]Erick Carvajal Barboza, Nishchal Shukla, Yiran Chen, Jiang Hu:
Machine Learning-Based Pre-Routing Timing Prediction with Reduced Pessimism. DAC 2019: 106 - [c144]Yu-Hung Huang, Zhiyao Xie, Guan-Qi Fang, Tao-Chun Yu, Haoxing Ren, Shao-Yun Fang, Yiran Chen, Jiang Hu:
Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model. DATE 2019: 180-185 - [c143]Chaofan Li, Sachin S. Sapatnekar, Jiang Hu:
Fast Mapping-Based High-Level Synthesis of Pipelined Circuits. ISQED 2019: 33-38 - [c142]Nithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Amr Abuellil, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran:
Breaking Analog Locking Techniques via Satisfiability Modulo Theories. ITC 2019: 1-10 - [c141]Lin Huang, I-Hong Hou, Sachin S. Sapatnekar, Jiang Hu:
Improving QoS for Global Dual-Criticality Scheduling on Multiprocessors. RTCSA 2019: 1-11 - [c140]Lang Feng, Jeff Huang, Jiang Hu, Abhijith Reddy:
FastCFI: Real-Time Control Flow Integrity Using FPGA Without Code Instrumentation. RV 2019: 221-238 - [p1]Deepashree Sengupta, Jiang Hu, Sachin S. Sapatnekar:
Error Analysis and Optimization in Approximate Arithmetic Circuits. Approximate Circuits 2019: 225-246 - 2018
- [j63]Zhaoxi Fang
Simultaneous Wireless Information and Power Transfer in Cellular Two-Way Relay Networks With Massive MIMO. IEEE Access 6: 29262-29270 (2018) - [j62]Li Fang
NextSV: a meta-caller for structural variants from low-coverage long-read sequencing data. BMC Bioinform. 19(1): 180:1-180:11 (2018) - [j61]Huaizhi Su, Jiang Hu, Hao Li:
Multi-scale performance simulation and effect analysis for hydraulic concrete submitted to leaching and frost. Eng. Comput. 34(4): 821-842 (2018) - [j60]Jiang Hu, Andre Milzarek, Zaiwen Wen, Yaxiang Yuan:
Adaptive Quadratically Regularized Newton Method for Riemannian Optimization. SIAM J. Matrix Anal. Appl. 39(3): 1181-1207 (2018) - [j59]Sanghoon Lee
A Built-In Self-Test and In Situ Analog Circuit Optimization Platform. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(10): 3445-3458 (2018) - [j58]Yujie Wang
The Cat and Mouse in Split Manufacturing. IEEE Trans. Very Large Scale Integr. Syst. 26(5): 805-817 (2018) - [j57]Wenbin Xu
A Simple Yet Efficient Accuracy-Configurable Adder Design. IEEE Trans. Very Large Scale Integr. Syst. 26(6): 1112-1125 (2018) - [c139]Lang Feng, Prabhakar Kudva, Dilma Da Silva, Jiang Hu:
Exploring Serverless Computing for Neural Network Training. IEEE CLOUD 2018: 334-341 - [c138]Jiang Hu:
Analyze the Factors of Firms to Rely on Internal and External Suppliers. AMCIS 2018 - [c137]Jiang Hu, Wei He:
Experience on Consumer Purchasing Decision-making: a Study of Anchoring Effects. AMCIS 2018 - [c136]Lin Huang, Youmeng Li, Sachin S. Sapatnekar, Jiang Hu:
Using imprecise computing for improved non-preemptive real-time scheduling. DAC 2018: 71:1-71:6 - [c135]Nithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran:
Towards provably-secure analog and mixed-signal locking against overproduction. ICCAD 2018: 7 - [c134]Weihong Cai, Yecong Chen, Jianquan Liu, Jiang Hu:
Analyzing Accessed Content Sequences with HDP-based Models. ICMSSP 2018: 142-149 - [c133]Hongxin Kong, Jun Cheng, Krishna R. Narayanan, Jiang Hu:
DUCER: a Fast and Lightweight Error Correction Scheme for In-Vehicle Network Communication. ICVES 2018: 1-6 - [c132]S. Y. Lee, Ming Kim Lim
Increasing Rate of Diffusion of Innovation in Supply Chain: Targeting the Early Adopters in UK Supply Chain. APMS (2) 2018: 209-214 - [c131]Jiang Hu, Ying Zhou, Yaoguang Wei, Stephen T. Quay, Lakshmi N. Reddy, Gustavo E. Téllez, Gi-Joon Nam:
Interconnect Optimization Considering Multiple Critical Paths. ISPD 2018: 132-138 - [c130]Lin Huang, I-Hong Hou, Sachin S. Sapatnekar, Jiang Hu:
Graceful Degradation of Low-Criticality Tasks in Multiprocessor Dual-Criticality Systems. RTNS 2018: 159-169 - [i1]Nithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran:
Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction. IACR Cryptol. ePrint Arch. 2018: 1064 (2018) - 2017
- [c129]Miguel I. Aguirre-Urreta, Jiang Hu, Mikko Rönkkö:
Polynomial Regression and Measurement Error: Implications for IS Research. AMCIS 2017 - [c128]Yujie Wang, Pu Chen, Jiang Hu, Jeyavijayan (JV) Rajendran:
Routing perturbation for enhanced security in split manufacturing. ASP-DAC 2017: 605-510 - [c127]He Zhou, Sunil P. Khatri, Jiang Hu, Frank Liu, Cliff C. N. Sze:
Fast and Highly Scalable Bayesian MDP on a GPU Platform. BCB 2017: 158-167 - [c126]Chaofan Li, Deepashree Sengupta, Farhana Sharmin Snigdha, Wenbin Xu, Jiang Hu, Sachin S. Sapatnekar
A quantifiable approach to approximate computing: special session. CASES 2017: 1:1-1:2 - [c125]Deepashree Sengupta, Farhana Sharmin Snigdha, Jiang Hu, Sachin S. Sapatnekar
SABER: Selection of Approximate Bits for the Design of Error Tolerant Circuits. DAC 2017: 72:1-72:6 - [c124]Yujie Wang, Tri Cao, Jiang Hu, Jeyavijayan Rajendran:
Front-end-of-line attacks in split manufacturing. ICCAD 2017: 1-8 - [c123]Lang Feng, Yujie Wang, Jiang Hu, Wai-Kei Mak, Jeyavijayan Rajendran:
Making split fabrication synergistically secure and manufacturable. ICCAD 2017: 313-320 - [c122]Lang Feng, Yujie Wang, Jiang Hu, Wai-Kei Mak, Jeyavijayan Rajendran:
Making split fabrication synergistically secure and manufacturable. ICCAD 2017: 321-328 - [c121]Hao He, Jiang Hu, Dilma Da Silva:
Enhancing Datacenter Resource Management through Temporal Logic Constraints. IPDPS 2017: 133-142 - [c120]Wenbin Xu, Sachin S. Sapatnekar
A simple yet efficient accuracy configurable adder design. ISLPED 2017: 1-6 - [c119]Lijia Sun, Yanxiang Yang, Jiang Hu, Dana Porter, Thomas H. Marek, Charles Hillyer:
Reinforcement Learning Control for Water-Efficient Agricultural Irrigation. ISPA/IUCC 2017: 1334-1341 - [c118]Yanxiang Yang, Lijia Sun, Jiang Hu, Dana Porter, Thomas H. Marek, Charles Hillyer:
A Reliable Soil Moisture Sensing Methodology for Agricultural Irrigation. ISPA/IUCC 2017: 1342-1349 - [c117]Jiafan Wang, Congyin Shi, Adriana C. Sanabria-Borbon, Edgar Sánchez-Sinencio, Jiang Hu:
Thwarting analog IC piracy via combinational locking. ITC 2017: 1-10 - [c116]Lijia Sun, Jiang Hu, Yang Liu, Lin Liu, Shiyan Hu:
A comparative study on neural network-based prediction of smart community energy consumption. SmartWorld/SCALCOM/UIC/ATC/CBDCom/IOP/SCI 2017: 1-8 - 2016
- [j56]Huaizhi Su, Zhiping Wen, Feng Wang, Jiang Hu
Dam structural behavior identification and prediction by using variable dimension fractal model and iterated function system. Appl. Soft Comput. 48: 612-620 (2016) - [j55]Jae-Yeon Won, Paul V. Gratz
Resource Sharing Centric Dynamic Voltage and Frequency Scaling for CMP Cores, Uncore, and Memory. ACM Trans. Design Autom. Electr. Syst. 21(4): 69:1-69:25 (2016) - [c115]He Zhou, Jiang Hu, Sunil P. Khatri, Frank Liu, Cliff C. N. Sze, Mohammadmahdi R. Yousefi:
GPU acceleration for Bayesian control of Markovian genetic regulatory networks. BHI 2016: 304-307 - [c114]Farhana Sharmin Snigdha, Deepashree Sengupta, Jiang Hu, Sachin S. Sapatnekar
Optimal design of JPEG hardware under the approximate computing paradigm. DAC 2016: 106:1-106:6 - [c113]Yujie Wang, Pu Chen, Jiang Hu, Jeyavijayan Rajendran:
The cat and mouse in split manufacturing. DAC 2016: 165:1-165:6 - [c112]Chaofan Li, Sachin S. Sapatnekar
Control synthesis and delay sensor deployment for efficient ASV designs. ICCAD 2016: 64 - [c111]Ang Lu, Hao He, Jiang Hu:
Proximity Optimization for Adaptive Circuit Design. ISPD 2016: 91-97 - 2015
- [j54]Azadeh Davoodi, Jiang Hu, Muhammet Mustafa Ozdal, Cliff C. N. Sze:
Guest Editorial: Special Section on Physical Design Techniques for Advanced Technology Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(4): 501 (2015) - [j53]Jae-Yeon Won, Hyunsurk Ryu, Tobi Delbrück, Junhaeng Lee, Jiang Hu:
Proximity Sensing Based on a Dynamic Vision Sensor for Mobile Devices. IEEE Trans. Ind. Electron. 62(1): 536-544 (2015) - [c110]Chaofan Li, Wei Luo, Sachin S. Sapatnekar
Joint precision optimization and high level synthesis for approximate computing. DAC 2015: 104:1-104:6 - [c109]Rohit Kumar, Bing Li, Yiren Shen, Ulf Schlichtmann, Jiang Hu:
Timing verification for adaptive integrated circuits. DATE 2015: 1587-1590 - [c108]Chia-Yu Wu, Helmut Graeb, Jiang Hu:
A pre-search assisted ILP approach to analog integrated circuit routing. ICCD 2015: 244-250 - [c107]Yiren Shen, Jiang Hu:
GPU acceleration for PCA-based statistical static timing analysis. ICCD 2015: 674-679 - [c106]Hao He, Jiafan Wang, Jiang Hu:
Collaborative gate implementation selection and adaptivity assignment for robust combinational circuits. ISLPED 2015: 122-127 - [c105]Jae-Yeon Won, Paul Gratz
Having your cake and eating it too: Energy savings without performance loss through resource sharing driven power management. ISLPED 2015: 255-260 - [c104]Jiafan Wang, Congyin Shi, Edgar Sánchez-Sinencio, Jiang Hu:
Built-In Self Optimization for Variation Resilience of Analog Filters. ISVLSI 2015: 656-661 - 2014
- [j52]Xi Chen, Jiang Hu, Ning Xu:
Regularity-constrained floorplanning for multi-core processors. Integr. 47(1): 86-95 (2014) - [c103]Jae-Yeon Won, Xi Chen, Paul Gratz
Up by their bootstraps: Online learning in Artificial Neural Networks for CMP uncore power management. HPCA 2014: 308-319 - [c102]Hao He, Gongming Yang, Jiang Hu:
Algorithms for power-efficient QoS in application specific NoCs. ISLPED 2014: 165-170 - [c101]Amrinder Singh, Jiang Hu:
Case studies on variation tolerant and low power design using planar asymmetric double gate transistor. MWSCAS 2014: 1021-1024 - [c100]Shalimar Rasheed, Paul V. Gratz
STORM: A Simple Traffic-Optimized Router Microarchitecture for Networks-on-Chip. NOCS 2014: 176-177 - 2013
- [j51]Huaizhi Su, Zhiping Wen, Feng Wang, Bowen Wei, Jiang Hu
Multifractal scaling behavior analysis for existing dams. Expert Syst. Appl. 40(12): 4922-4933 (2013) - [j50]Jiang Hu, Cheng-Kok Koh:
Guest editorial: Special section on cross-domain physical optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(2): 173-174 (2013) - [j49]Xi Chen, Zheng Xu, Hyungjun Kim, Paul Gratz
In-network monitoring and control policy for DVFS of CMP networks-on-chip and last level caches. ACM Trans. Design Autom. Electr. Syst. 18(4): 47:1-47:21 (2013) - [j48]Kyu-Nam Shim, Jiang Hu, José Silva-Martínez:
Dual-Level Adaptive Supply Voltage System for Variation Resilience. IEEE Trans. Very Large Scale Integr. Syst. 21(6): 1041-1052 (2013) - [j47]Kyu-Nam Shim, Jiang Hu:
Boostable Repeater Design for Variation Resilience in VLSI Interconnects. IEEE Trans. Very Large Scale Integr. Syst. 21(9): 1619-1631 (2013) - [c99]Xi Chen, Zheng Xu, Hyungjun Kim, Paul V. Gratz
Dynamic voltage and frequency scaling for shared resources in multicore processor designs. DAC 2013: 114:1-114:7 - [c98]David Kadjo, Hyungjun Kim, Paul Gratz
Power gating with block migration in chip-multiprocessor last-level caches. ICCD 2013: 93-99 - [c97]Gongming Yang, Hao He, Jiang Hu:
Resource allocation algorithms for guaranteed service in application-specific NoCs. ICCD 2013: 483-486 - 2012
- [j46]Jiang Hu, Cheng-Kok Koh:
Guest Editorial Special Section on the 2011 International Symposium on Physical Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(2): 165-166 (2012) - [j45]Muhammet Mustafa Ozdal, Steven M. Burns, Jiang Hu:
Algorithms for Gate Sizing and Device Parameter Selection for High-Performance Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(10): 1558-1571 (2012) - [c96]Kyu-Nam Shim, Jiang Hu:
A low overhead built-in delay testing with voltage and frequency adaptation for variation resilience. DFT 2012: 170-177 - [c95]Qiong Zhao, Jiang Hu:
Track assignment considering crosstalk-induced performance degradation. ICCD 2012: 506-507 - [c94]Xi Chen, Zheng Xu, Hyungjun Kim, Paul Gratz
In-network Monitoring and Control Policy for DVFS of CMP Networks-on-Chip and Last Level Caches. NOCS 2012: 43-50 - [c93]Yimei Kang, Yang Han, Jiang Hu:
A node scheduling based on partition for WSN. WTS 2012: 1-6 - [e2]Jiang Hu, Cheng-Kok Koh:
International Symposium on Physical Design, ISPD'12, Napa, CA, USA, March 25-28, 2012. ACM 2012, ISBN 978-1-4503-1167-0 [contents] - 2011
- [j44]Yifang Liu, Rupesh S. Shelar, Jiang Hu:
Simultaneous Technology Mapping and Placement for Delay Minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(3): 416-426 (2011) - [j43]Yifang Liu, Jiang Hu:
GPU-Based Parallelization for Fast Circuit Optimization. ACM Trans. Design Autom. Electr. Syst. 16(3): 24:1-24:14 (2011) - [j42]Mohammad Asad R. Chaudhry, Zakia Asad, Alexander Sprintson
Efficient Congestion Mitigation Using Congestion-Aware Steiner Trees and Network Coding Topologies. VLSI Design 2011: 892310:1-892310:9 (2011) - [c92]Muhammet Mustafa Ozdal, Steven M. Burns, Jiang Hu:
Gate sizing and device technology selection algorithms for high-performance industrial designs. ICCAD 2011: 724-731 - [c91]Yimei Kang, Guan Wang, Jiang Hu:
A bilinear interpolation mean shift small target tracking algorithm. ICSPCS 2011: 1-6 - [c90]Xi Chen, Jiang Hu, Ning Xu:
Regularity-constrained floorplanning for multi-core processors. ISPD 2011: 99-106 - [c89]Yi-Le Huang, Jiang Hu, Weiping Shi:
Lagrangian relaxation for gate implementation selection. ISPD 2011: 167-174 - [c88]Kyu-Nam Shim, Jiang Hu:
Transient and fine-grained voltage adaptation for variation resilience in VLSI interconnects. ISQED 2011: 80-86 - [c87]Yimei Kang, Guan Wang, Jiang Hu:
A mean shift based small target tracking algorithm in colored video. SoCPaR 2011: 407-412 - [e1]Yao-Wen Chang, Jiang Hu:
Proceedings of the 2011 International Symposium on Physical Design, ISPD 2011, Santa Barbara, California, USA, March 27-30, 2011. ACM 2011, ISBN 978-1-4503-0550-1 [contents] - 2010
- [j41]Yifang Liu, Jiang Hu:
A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(2): 223-234 (2010) - [j40]Xiaoji Ye, Peng Li, Min Zhao, Rajendran Panda, Jiang Hu:
Scalable Analysis of Mesh-Based Clock Distribution Networks Using Application-Specific Reduced Order Modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(9): 1342-1353 (2010) - [j39]Ganesh Venkataraman, Zhuo Feng, Jiang Hu, Peng Li:
Combinatorial Algorithms for Fast Clock Mesh Optimization. IEEE Trans. Very Large Scale Integr. Syst. 18(1): 131-141 (2010) - [j38]Shiyan Hu, Patrik Shah, Jiang Hu:
Pattern Sensitive Placement Perturbation for Manufacturability. IEEE Trans. Very Large Scale Integr. Syst. 18(6): 1002-1006 (2010) - [j37]Rupak Samanta, Jiang Hu, Peng Li:
Discrete Buffer and Wire Sizing for Link-Based Non-Tree Clock Networks. IEEE Trans. Very Large Scale Integr. Syst. 18(7): 1025-1035 (2010) - [j36]Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu:
An Effective Gated Clock Tree Design Based on Activity and Register Aware Placement. IEEE Trans. Very Large Scale Integr. Syst. 18(12): 1639-1648 (2010) - [c86]Yaoguang Wei, Jiang Hu, Frank Liu, Sachin S. Sapatnekar
Physical design techniques for optimizing RTA-induced variations. ASP-DAC 2010: 745-750 - [c85]Tanuj Jindal, Charles J. Alpert, Jiang Hu, Zhuo Li, Gi-Joon Nam, Charles B. Winn:
Detecting tangled logic structures in VLSI netlists. DAC 2010: 603-608 - [c84]Fan Yang, Yici Cai, Qiang Zhou, Jiang Hu:
SAT based multi-net rip-up-and-reroute for manufacturing hotspot removal. DATE 2010: 1369-1372 - [c83]Yifang Liu, Yu Yang, Jiang Hu:
Clustering-based simultaneous task and voltage scheduling for NoC systems. ICCAD 2010: 277-283 - [c82]Venkata Rajesh Mekala, Yifang Liu, Xiaoji Ye, Jiang Hu, Peng Li:
Accurate clock mesh sizing via sequential quadraticprogramming. ISPD 2010: 135-142 - [c81]Kyu-Nam Shim, Jiang Hu, José Silva-Martínez:
A dual-level adaptive supply voltage system for variation resilience. ISQED 2010: 38-43 - [c80]Weixiang Shen, Yici Cai, Wei Chen, Yongqiang Lu, Qiang Zhou, Jiang Hu:
Useful clock skew optimization under a multi-corner multi-mode design framework. ISQED 2010: 62-68
2000 – 2009
- 2009
- [j35]Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu:
A single layer zero skew clock routing in X architecture. Sci. China Ser. F Inf. Sci. 52(8): 1466-1475 (2009) - [j34]Shiyan Hu, Jiang Hu:
A fast general slew constrained minimum cost buffering algorithm. Microelectron. J. 40(10): 1482-1486 (2009) - [j33]Shiyan Hu
Gate Sizing for Cell-Library-Based Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(6): 818-825 (2009) - [j32]Yang Liu, Tong Zhang, Jiang Hu:
Design of Voltage Overscaled Low-Power Trellis Decoders in Presence of Process Variations. IEEE Trans. Very Large Scale Integr. Syst. 17(3): 439-443 (2009) - [j31]Rupak Samanta, Ganesh Venkataraman, Jiang Hu:
Clock Buffer Polarity Assignment for Power Noise Reduction. IEEE Trans. Very Large Scale Integr. Syst. 17(6): 770-780 (2009) - [c79]Yifang Liu, Jiang Hu:
GPU-based parallelization for fast circuit optimization. DAC 2009: 943-946 - [c78]Pratik J. Shah, Jiang Hu:
Impact of lithography-friendly circuit layout. ACM Great Lakes Symposium on VLSI 2009: 385-388 - [c77]Yifang Liu, Jiang Hu:
A new algorithm for simultaneous gate sizing and threshold voltage assignment. ISPD 2009: 27-34 - 2008
- [j30]Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu:
Low Power Gated Clock Tree Driven Placement. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(2): 595-603 (2008) - [j29]Ke Cao, Jiang Hu:
ASIC design flow considering lithography-induced effects. IET Circuits Devices Syst. 2(1): 23-29 (2008) - [j28]Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu:
Zero skew clock routing in X-architecture based on an improved greedy matching algorithm. Integr. 41(3): 426-438 (2008) - [j27]Cheng Zhuo, Jiang Hu, Min Zhao, Kangsheng Chen:
Power Grid Analysis and Optimization Using Algebraic Multigrid. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(4): 738-751 (2008) - [j26]Uday Padmanabhan, Janet Meiling Wang, Jiang Hu:
Robust Clock Tree Routing in the Presence of Process Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(8): 1385-1397 (2008) - [j25]Yifang Liu, Jiang Hu, Weiping Shi:
Buffering Interconnect for Multicore Processor Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(12): 2183-2196 (2008) - [c76]Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian:
Low power clock buffer planning methodology in F-D placement for large scale circuit design. ASP-DAC 2008: 370-375 - [c75]Sridhar Varadan, Janet Meiling Wang, Jiang Hu:
Handling partial correlations in yield prediction. ASP-DAC 2008: 543-548 - [c74]Nimay Shah, Rupak Samanta, Ming Zhang, Jiang Hu, Duncan Walker:
Built-In Proactive Tuning System for Circuit Aging Resilience. DFT 2008: 96-104 - [c73]Yifang Liu, Rupesh S. Shelar, Jiang Hu:
Delay-optimal simultaneous technology mapping and placement with applications to timing optimization. ICCAD 2008: 101-106 - [c72]Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu:
Gate planning during placement for gated clock network. ICCD 2008: 128-133 - [c71]Yifang Liu, Jiang Hu, Weiping Shi:
Multi-scenario buffer insertion in multi-core processor designs. ISPD 2008: 15-22 - [c70]Rupak Samanta, Jiang Hu, Peng Li:
Discrete buffer and wire sizing for link-based non-tree clock networks. ISPD 2008: 175-181 - [c69]Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu:
Activity and register placement aware gated clock network design. ISPD 2008: 182-189 - [c68]Rupak Samanta, Ganesh Venkataraman, Nimay Shah, Jiang Hu:
Elastic Timing Scheme for Energy-Efficient and Robust Performance. ISQED 2008: 537-542 - [c67]Xiaoji Ye, Min Zhao, Rajendran Panda, Peng Li, Jiang Hu:
Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding. ISQED 2008: 627-632 - [r3]Jiang Hu, Zhuo Li, Shiyan Hu:
Buffer Insertion Basics. Handbook of Algorithms for Physical Design Automation 2008 - [r2]Jiang Hu, Gabriel Robins, Cliff C. N. Sze:
Timing-Driven Interconnect Synthesis. Handbook of Algorithms for Physical Design Automation 2008 - [r1]Jiang Hu, Cliff C. N. Sze:
Buffering in the Layout Environment. Handbook of Algorithms for Physical Design Automation 2008 - 2007
- [j24]Jiang Hu, Patrick H. Madden:
Guest Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(4): 617-618 (2007) - [j23]Bor-Yiing Su, Yao-Wen Chang
An Exact Jumper-Insertion Algorithm for Antenna Violation Avoidance/Fixing Considering Routing Obstacles. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(4): 719-733 (2007) - [j22]Chin Ngai Sze, Charles J. Alpert, Jiang Hu, Weiping Shi:
Path-Based Buffer Insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7): 1346-1355 (2007) - [j21]Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Chin Ngai Sze:
Fast Algorithms for Slew-Constrained Minimum Cost Buffering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(11): 2009-2022 (2007) - [j20]Ganesh Venkataraman, Jiang Hu, Frank Liu:
Integrated Placement and Skew Optimization for Rotary Clocking. IEEE Trans. Very Large Scale Integr. Syst. 15(2): 149-158 (2007) - [j19]Shiyan Hu, Qiuyang Li, Jiang Hu, Peng Li:
Utilizing Redundancy for Timing Critical Interconnect. IEEE Trans. Very Large Scale Integr. Syst. 15(10): 1067-1080 (2007) - [j18]Ke Cao, Jiang Hu, Mosong Cheng:
Wire Sizing and Spacing for Lithographic Printability and Timing Optimization. IEEE Trans. Very Large Scale Integr. Syst. 15(12): 1332-1340 (2007) - [c66]Bao Liu, Andrew B. Kahng, Xu Xu, Jiang Hu, Ganesh Venkataraman:
A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield. ASP-DAC 2007: 24-31 - [c65]Jiang Hu, Andi Winterboer, Clifford Nass, Johanna D. Moore, Rebecca Illowsky:
Context & usability testing: user-modeled information presentation in easy and difficult driving conditions. CHI 2007: 1343-1346 - [c64]Shiyan Hu, Mahesh Ketkar, Jiang Hu:
Gate Sizing For Cell Library-Based Designs. DAC 2007: 847-852 - [c63]Shiyan Hu, Jiang Hu:
Unified adaptivity optimization of clock and logic signals. ICCAD 2007: 125-130 - [c62]Cheng Zhuo, Huafeng Zhang, Rupak Samanta, Jiang Hu, Kangsheng Chen:
Modeling, optimization and control of rotary traveling-wave oscillator. ICCAD 2007: 476-480 - [c61]Xiaoji Ye, Peng Li, Min Zhao, Rajendran Panda, Jiang Hu:
Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding. ICCAD 2007: 627-631 - [c60]Andi Winterboer, Jiang Hu, Johanna D. Moore, Clifford Nass:
The influence of user tailoring and cognitive load on user performance in spoken dialogue systems. INTERSPEECH 2007: 2717-2720 - [c59]Shiyan Hu, Jiang Hu:
Pattern sensitive placement for manufacturability. ISPD 2007: 27-34 - [c58]Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Weiping Shi:
An Efficient Algorithm for RLC Buffer Insertion. ISQED 2007: 171-175 - [c57]Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu:
Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture. ISQED 2007: 299-304 - [c56]Yang Liu, Tong Zhang, Jiang Hu:
Soft Clock Skew Scheduling for Variation-Tolerant Signal Processing Circuits: A Case Study of Viterbi Decoders. ISQED 2007: 749-754 - [c55]Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu:
Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction. ISVLSI 2007: 383-388 - [c54]Ganesh Venkataraman, Jiang Hu:
A Placement Methodology for Robust Clocking. VLSI Design 2007: 881-886 - 2006
- [j17]Di Wu, Jiang Hu, Rabi N. Mahapatra:
Antenna Avoidance in Layer Assignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(4): 734-738 (2006) - [j16]Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar
Accurate estimation of global buffer delay within a floorplan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 1140-1145 (2006) - [j15]Anand Rajaram, Jiang Hu, Rabi N. Mahapatra:
Reducing clock skew variability via crosslinks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 1176-1182 (2006) - [j14]Anand Rajaram, Bing Lu, Jiang Hu, Rabi N. Mahapatra, Wei Guo:
Analytical bound for unwanted clock skew due to wire width variation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9): 1869-1876 (2006) - [c53]Mike Brzozowski, Kendra Carattini, Scott R. Klemmer, Patrick Mihelich, Jiang Hu, Andrew Y. Ng:
groupTime: preference based group scheduling. CHI 2006: 1047-1056 - [c52]Jamie Pearson, Jiang Hu, Holly P. Branigan
Adaptive language behavior in HCI: how expectations and beliefs about a system affect users' word choice. CHI 2006: 1177-1180 - [c51]Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Cliff C. N. Sze:
Fast algorithms for slew constrained minimum cost buffering. DAC 2006: 308-313 - [c50]Shiyan Hu, Qiuyang Li, Jiang Hu, Peng Li:
Steiner network construction for timing critical nets. DAC 2006: 379-384 - [c49]Ke Cao, Sorin Dobre, Jiang Hu:
Standard cell characterization considering lithography induced variations. DAC 2006: 801-804 - [c48]Ganesh Venkataraman, Jiang Hu, Frank Liu, Cliff C. N. Sze:
Integrated placement and skew optimization for rotary clocking. DATE 2006: 756-761 - [c47]Min-Seok Kim, Jiang Hu:
Associative skew clock routing for difficult instances. DATE 2006: 762-767 - [c46]Cheng Zhuo, Jiang Hu, Min Zhao, Kangsheng Chen:
Fast decap allocation based on algebraic multigrid. ICCAD 2006: 107-111 - [c45]Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Zhuo Li, Weiping Shi:
A new RLC buffer insertion algorithm. ICCAD 2006: 553-557 - [c44]Rupak Samanta, Ganesh Venkataraman, Jiang Hu:
Clock buffer polarity assignment for power noise reduction. ICCAD 2006: 558-562 - [c43]Ganesh Venkataraman, Zhuo Feng, Jiang Hu, Peng Li:
Combinatorial algorithms for fast clock mesh optimization. ICCAD 2006: 563-567 - [c42]Weixiang Shen, Yici Cai, Jiang Hu, Xianlong Hong, Bing Lu:
High performance clock routing in X-architecture. ISCAS 2006 - [c41]Bor-Yiing Su, Yao-Wen Chang, Jiang Hu:
An optimal jumper insertion algorithm for antenna avoidance/fixing on general routing trees with obstacles. ISPD 2006: 56-63 - [c40]Uday Padmanabhan, Janet Meiling Wang, Jiang Hu:
Statistical clock tree routing for robustness to process variations. ISPD 2006: 149-156 - [c39]Zhuo Feng, Peng Li, Jiang Hu:
Efficient Model Update for General Link-Insertion Networks. ISQED 2006: 43-50 - [c38]Cheng Zhuo, Jiang Hu, Kangsheng Chen:
An Improved AMG-based Method for Fast Power Grid Analysis. ISQED 2006: 290-295 - [c37]Yang Liu, Tong Zhang, Jiang Hu:
Low Power Trellis Decoder with Overscaled Supply Voltage. SiPS 2006: 205-208 - 2005
- [j13]Yongqiang Lu, Chin Ngai Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu:
Navigating Register Placement for Low Power Clock Network Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3405-3411 (2005) - [j12]Rishi Chaturvedi, Jiang Hu:
An efficient merging scheme for prescribed skew clock routing. IEEE Trans. Very Large Scale Integr. Syst. 13(6): 750-754 (2005) - [c36]Zhuo Li, Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi:
Making fast buffer insertion even faster via approximation techniques. ASP-DAC 2005: 13-18 - [c35]Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, Jiang Hu, Yongqiang Lu:
Clock network minimization methodology based on incremental placement. ASP-DAC 2005: 99-102 - [c34]Ke Cao, Puneet Dhawan, Jiang Hu:
Library cell layout with Alt-PSM compliance and composability. ASP-DAC 2005: 216-219 - [c33]Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu:
Register placement for low power clock network. ASP-DAC 2005: 588-593 - [c32]Ganesh Venkataraman, Cliff C. N. Sze, Jiang Hu:
Skew scheduling and clock routing for improved tolerance to process variations. ASP-DAC 2005: 594-599 - [c31]Di Wu, Jiang Hu, Min Zhao, Rabi N. Mahapatra:
Timing driven track routing considering coupling capacitance. ASP-DAC 2005: 1156-1159 - [c30]Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu:
Navigating registers in placement for clock network minimization. DAC 2005: 176-181 - [c29]Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi:
Path based buffer insertion. DAC 2005: 509-514 - [c28]Di Wu, Ganesh Venkataraman, Jiang Hu, Quiyang Li, Rabi N. Mahapatra:
DiCER: distributed and cost-effective redundancy for variation tolerance. ICCAD 2005: 393-397 - [c27]Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, Peng Li, Sunil P. Khatri, Anand Rajaram, Patrick McGuinness, Charles J. Alpert:
Practical techniques to reduce skew and its variations in buffered clock networks. ICCAD 2005: 592-596 - [c26]Qianying Wang, Clifford Nass, Jiang Hu:
Natural Language Query vs. Keyword Search: Effects of Task Complexity on Search Performance, Participant Perceptions, and Preferences. INTERACT 2005: 106-116 - [c25]Jiang Hu, Mike Brzozowski:
Preference-Based Group Scheduling. INTERACT 2005: 990-993 - [c24]Di Wu, Jiang Hu, Rabi N. Mahapatra:
Coupling aware timing optimization and antenna avoidance in layer assignment. ISPD 2005: 20-27 - [c23]Anand Rajaram, David Z. Pan, Jiang Hu:
Improved algorithms for link-based non-tree clock networks for skew variability reduction. ISPD 2005: 55-62 - [c22]Qianying Wang, Jiang Hu, Clifford Nass:
Natural Language Interface Put in Perspective: Interaction of Search Method and Task Complexity. NLUCS 2005: 3-12 - 2004
- [j11]Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay:
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(1): 136-141 (2004) - [j10]Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay, Cliff C. N. Sze:
Porosity-aware buffered Steiner tree construction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(4): 517-526 (2004) - [j9]Haihua Su, Jiang Hu, Sachin S. Sapatnekar
A methodology for the simultaneous design of supply and signal networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(12): 1614-1624 (2004) - [c21]Di Wu, Jiang Hu, Rabi N. Mahapatra, Min Zhao:
Layer assignment for crosstalk risk minimization. ASP-DAC 2004: 159-162 - [c20]Cliff C. N. Sze, Jiang Hu, Charles J. Alpert:
A place and route aware buffered Steiner tree construction. ASP-DAC 2004: 355-360 - [c19]Anand Rajaram, Jiang Hu, Rabi N. Mahapatra:
Reducing clock skew variability via cross links. DAC 2004: 18-23 - [c18]Charles J. Alpert, Milos Hrkic, Jiang Hu, Stephen T. Quay:
Fast and flexible buffer trees that navigate the physical layout environment. DAC 2004: 24-29 - [c17]V. Seth, Min Zhao, Jiang Hu:
Exploiting level sensitive latches in wire pipelining. ICCAD 2004: 283-290 - [c16]Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar
Accurate estimation of global buffer delay within a floorplan. ICCAD 2004: 706-711 - [c15]Rishi Chaturvedi, Jiang Hu:
Buffered Clock Tree for High Quality IC Design. ISQED 2004: 381-386 - 2003
- [j8]Jiang Hu, Charles J. Alpert, Stephen T. Quay, Gopal Gandham:
Buffer insertion with adaptive blockage avoidance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(4): 492-498 (2003) - [j7]Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar
A practical methodology for early buffer and wire resource allocation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(5): 573-583 (2003) - [c14]Anand Rajaram, Bing Lu, Wei Guo, Rabi N. Mahapatra, Jiang Hu:
Analytical Bound for Unwanted Clock Skew due to Wire Width Variation. ICCAD 2003: 401-407 - [c13]Rishi Chaturvedi, Jiang Hu:
A Simple Yet Effective Merging Scheme for Prescribed-Skew Clock Routing. ICCD 2003: 282- - [c12]Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay:
Porosity aware buffered steiner tree construction. ISPD 2003: 158-165 - [c11]Bing Lu, Jiang Hu, Gary Ellis, Haihua Su:
Process variation aware clock tree routing. ISPD 2003: 174-181 - 2002
- [j6]Jiang Hu, Sachin S. Sapatnekar
A timing-constrained simultaneous global routing algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(9): 1025-1036 (2002) - [j5]Jiang Hu, Sachin S. Sapatnekar
Performance Driven Global Routing Through Gradual Refinement. VLSI Design 15(3): 595-604 (2002) - [c10]Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif:
Congestion-driven codesign of power and signal networks. DAC 2002: 64-69 - [c9]Jiang Hu, Charles J. Alpert, Stephen T. Quay, Gopal Gandham:
Buffer insertion with adaptive blockage avoidance. ISPD 2002: 92-97 - [c8]Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay:
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. ISPD 2002: 104-109 - 2001
- [j4]Jiang Hu, Sachin S. Sapatnekar
A survey on multi-net global routing for integrated circuits. Integr. 31(1): 1-49 (2001) - [j3]Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar
Steiner tree optimization for buffers, blockages, and bays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(4): 556-562 (2001) - [c7]Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia:
A Practical Methodology for Early Buffer and Wire Resource Allocation. DAC 2001: 189-194 - [c6]Jiang Hu, Sachin S. Sapatnekar:
Performance Driven Global Routing Through Gradual Refinement. ICCD 2001: 481-483 - [c5]Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar:
Steiner tree optimization for buffers. Blockages and bays. ISCAS (5) 2001: 399-402 - [c4]Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia:
Buffered Steiner trees for difficult instances. ISPD 2001: 4-9 - 2000
- [j2]Jiang Hu, Sachin S. Sapatnekar
Algorithms for non-Hanan-based optimization for VLSI interconnectunder a higher-order AWE model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(4): 446-458 (2000) - [c3]Jiang Hu, Sachin S. Sapatnekar:
A Timing-Constrained Algorithm for Simultaneous Global Routing of Multiple Nets. ICCAD 2000: 99-103
1990 – 1999
- 1999
- [j1]Huibo Hou, Jiang Hu, Sachin S. Sapatnekar
Non-Hanan routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(4): 436-444 (1999) - [c2]Jiang Hu, Sachin S. Sapatnekar:
FAR-DS: Full-Plane AWE Routing with Driver Sizing. DAC 1999: 84-89 - [c1]Jiang Hu, Sachin S. Sapatnekar:
Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model. ISPD 1999: 133-138
Coauthor Index
Paul Gratz
aka: Paul V. Gratz
aka: Paul V. Gratz
Jeyavijayan Rajendran
aka: Jeyavijayan (JV) Rajendran
aka: Jeyavijayan (JV) Rajendran
[j98] [j91] [j90] [c194] [c189] [j81] [j79] [c178] [c175] [c171] [c170] [c168] [c162] [c159] [c158] [c153] [c151] [i8] [j68] [j67] [c148] [c146] [c143] [c141] [p1] [j57] [c136] [c130] [c126] [c125] [c120] [c114] [c112] [c110] [c86] [j16] [j9] [c16] [j7] [j6] [j5] [c10] [j4] [j3] [c7] [c6] [c5] [c4] [j2] [c3] [j1] [c2] [c1]
Arvind K. Sharma
aka: Arvind Kumar Sharma
aka: Arvind Kumar Sharma
Cliff C. N. Sze
aka: Chin Ngai Sze
aka: Chin Ngai Sze
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