Chisel: A Modern Hardware Design Language

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Scala based HDL

Cask: a Scala HTTP micro-framework. Cask makes it easy to set up a website, backend server, or REST API using Scala

Common RTL blocks used in SiFive's projects

A dynamic verification library for Chisel.

Time-sensitive affine types for predictable hardware generation

Antmicro's fast, vendor-neutral DMA IP in Chisel

HDMI interface for GameBoy DMG

(System)Verilog to Chisel translator

A tiny POWER Open ISA soft processor written in Chisel

A RISC-V Core (RV32I) written in Chisel HDL

Lipsi: Probably the Smallest Processor in the World

ElemRV - End-to-end Open-Source RISC-V Microcontroller

For contributions of Chisel IP to the chisel community.

HDMI core in Chisel HDL

Chisel HDL example applications

Wishbone plumbing written in Chisel3

IEEE binary 32 floating-point division hardware in Chisel based on Harmonized Parabolic Synthesis with 6 pipeline stages.

Implementation of low-level hardware arithmatic operations in Chisel

Hardware CRC implementation in Chisel

Sound effects and music related hardware (in Chisel)

Chisel presentation FPGA Forum 2020

Drive MDIO phy interface with a Chisel component

reimplementation of the serv core in Chisel (https://github.com/olofk/serv)