VHDL 2008/93/87 simulator

A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the fut…

Open Logic FPGA Standard Library

A huge VHDL library for FPGA and digital ASIC development

UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improv…

VHDL synthesis (based on ghdl)

Game Boy hardware research

An open-source GBA consolizer.

Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project

A VHDL UART for communicating over a serial link with an FPGA

Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)

Portable HyperRAM controller

HDMI Out VHDL code for 7-series Xilinx FPGAs

Wishbone to AXI bridge (VHDL)

Alternative Logic16 Firmware

An open-source VHDL library for FPGA design.

Tests to evaluate the support of VHDL 2008 and VHDL 2019 features

VHDL String Formatting Library

A bit-serial CPU

Examples and design pattern for VHDL verification

Bonfire SoC running on FireAnt FPGA Board

Utilities for Avalon Memory Map

Blinking Led Project

Synthesizable VHDL models for HiL Simulation

Some example circuits written in VHDL for Terasic DE0-Nano FPGA board.

A True Random Number Generator in VHDL.

A VHDL implementation of VirtualWire/RadioHead