Source code for the X Recommendation Algorithm

Open-source high-performance RISC-V processor

Chisel: A Modern Hardware Design Language

Rocket Chip Generator

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

SonicBOOM: The Berkeley Out-of-Order Machine

FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility

Flexible Intermediate Representation for RTL

Simple RISC-V 3-stage Pipeline in Chisel

Lab exercises for Chisel in the digital electronics 2 course at DTU

high-performance RTL simulator

Alternative algorithm for algebraic subtyping.

UCLID5: formal modeling, verification, and synthesis of computational systems

(System)Verilog to Chisel translator

Course on Metaprogramming

The timenorm library provides models for finding natural language expressions of dates and times and converting them to a normalized form.

Examples of Automatic Differentiation (AD) in many different languages and systems

Agile Hardware Design Course