opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Must-have verilog systemverilog modules

HDL libraries and projects

The Ultra-Low Power RISC-V Core

Verilog PCI express components

An Open-source FPGA IP Generator

RISC-V XV6/Linux SoC, marchID: 0x2b

Various HDL (Verilog) IP Cores

HDLBits website practices & solutions

A High-performance Timing Analysis Tool for VLSI Systems

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

VRoom! RISC-V CPU

Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.

OpenXuantie - OpenC906 Core

FuseSoC-based SoC for VeeR EH1 and EL2

SystemVerilog synthesis tool

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.

NCTU 2021 Spring Integrated Circuit Design Laboratory

High Frequency Trading using Vivado HLS

Universal Memory Interface (UMI)

Spring 2023 NYCU (prev. NCTU) Integrated Circuit Design Laboratory (ICLab)

An open-source benchmark for generating design RTL with natural language

FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool

Introductory course into static timing analysis (STA).

This is the repository for the IEEE version of the book

MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design

Recommended coding standard of Verilog and SystemVerilog.