A minimal GPU design in Verilog to learn how GPUs work from the ground up

Verilator open-source SystemVerilog simulator and lint system

OpenTitan: Open source silicon root of trust

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Common SystemVerilog components

BaseJump STL: A Standard Template Library for SystemVerilog

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional cache…

Verilog evaluation benchmark for large language model

Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.

Tile based architecture designed for computing efficiency, scalability and generality

Verilog/SystemVerilog Guide

Simple UVM environment for experimenting with Verilator.

This repository is compilation of basics of System Verilog Assertions in context of formal verification