FPGA Verilog RTL 설계하며 얻은 직관과 경험에 대한 정리본

Cryptography hardware/software engineering portfolio

ML-DSA polynomial multiplication on ESP32-S3 using Kronecker+ and the RSA MODMULT accelerator

Ibex RV32 custom-instruction integration and PQC bare-metal porting experiments with Verilator

C++ and CUDA experiments for LEA-CBC, LEA-GCM, table-based GHASH, and parallel authenticated encryption

Configurable radix-2/radix-3 NTT accelerator RTL for lattice-based post-quantum cryptography

C big-integer arithmetic library and educational fixed-width ECDH implementation

Zynq FPGA/software co-design for NCC-Sign with NTT, polynomial multiplication, and Keccak acceleration

CUDA implementation accompanying the 2025 ICT Express paper on fully parallel AES-GCM and GHASH

Personal Verilog solutions and Korean study notes for HDLBits exercises

Educational software cryptographic module with ARIA, SHA-3/HMAC, Hash_DRBG, P-256 ECDH, ML-KEM-768, self-tests, integrity checks, and state enforcement

Self-contained Falcon-512/1024 implementation and gprof study of KeyGen, Sign, and Verify (-O0 vs -O3)