PicoRV32 - A Size-Optimized RISC-V CPU

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

RTL, Cmodel, and testbench for NVDLA

IC design and development should be faster，simpler and more reliable

Verilog AXI components for FPGA implementation

RISC-V CPU Core (RV32IM)

A small, light weight, RISC CPU soft core

OpenXuantie - OpenC910 Core

Bus bridges and other odds and ends

RISC-V Formal Verification Framework

mor1kx - an OpenRISC 1000 processor IP core

Opensource DDR3 Controller

Some Hardware Architectures for GEMM

SystemVerilog synthesis tool

EPFL logic synthesis benchmarks

Fearless hardware design

RISC-V Formal Verification Framework

Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。

An open-source benchmark for generating design RTL with natural language

Pano Logic G2 Reverse Engineering Project

OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph level prediction problems in chip design.

IDEA project source files

Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks

Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.

Plugins for Yosys developed as part of the F4PGA project.

MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

A collection of big designs to run post-synthesis simulations with yosys

Parameterized Booth Multiplier in Verilog 2001