All pull requests

Pull requests

• [ImportVerilog] Drop unreachable tristate prim error

  #11164·TaoBi22 opened Sep 24, 2026Contributor·

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• [ImportVerilog] Refactor delayed prim assignment into shared helper

  #11162·TaoBi22 opened Sep 24, 2026Contributor·

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• [NFC][ImportVerilog] Drop a few unnecessary includes

  #11161·TaoBi22 opened Sep 24, 2026Contributor·

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• [PyCDE] Emit type aliases in an sv.package

  #11158·teqdruid opened Sep 24, 2026Contributor·2/2·

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  5

• [ESI][Cosim] Order directory sources by ExportVerilog's filelist

  #11157·teqdruid opened Sep 24, 2026Contributor·1/2·

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  1

• [ESI] ChannelArbiter: add wide_fanin timing structures

  ESI
  #11155·teqdruid opened Sep 23, 2026Contributor·

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  8

• [SV] Add core !sv.net<T> and !sv.var<T> type support

  #11154·okekayode opened Sep 23, 2026Contributor·

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  8

• [Arc] Fix aggregate feedback handling in enable inference

  #11152·hovhannes-96 opened Sep 23, 2026Contributor·

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  1

• [AXI4] Add cdc op

  #11147·TaoBi22 opened Sep 21, 2026Contributor·2/2·

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  1

• [AXI4] Add cut op

  #11146·TaoBi22 opened Sep 21, 2026Contributor·1/2·

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  1

• [MooreToCore][LLHD] Support dynamic part-select writes to packed structs

  #11142·liW-J opened Sep 20, 2026·

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  1

• [ExportVerilog] Change hw.union padding to match bitcast layout

  ExportVerilog
  #11135·fzi-hielscher opened Sep 16, 2026Contributor·

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  1

  10

• [ImportVerilog] Support string casts to packed arrays

  #11134·dagronlund opened Sep 16, 2026·

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• [ImportVerilog] Support concurrent cover properties and sequences

  #11132·dagronlund opened Sep 16, 2026·

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  1

  1

• [ImportVerilog] Support assignment patterns as assignment destinations

  #11131·dagronlund opened Sep 16, 2026·

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  5

• [ImportVerilog] Resolve hierarchical outputs from expanded interfaces

  #11130·dagronlund opened Sep 16, 2026·

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  1

  10

• [ImportVerilog] Support connected interface-array ports

  #11129·dagronlund opened Sep 16, 2026·

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  1

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• [AXI4ToHW] Lower AXI4 ports

  #11125·TaoBi22 opened Sep 16, 2026Contributor·

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  2

• [FIRRTL] Bounce non-connect users of dropped zero-width instance ports

  #11118·arcusbuilds opened Sep 15, 2026·

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  1

• [Handshake] Fix argument indexing in LowerExtmemToHW with several memories

  #11112·kevinyuan opened Sep 12, 2026Contributor·

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  5

• [ImportVerilog] Support fixed-size aggregates in streaming operators

  #11110·SathsaraGeeth opened Sep 12, 2026·

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• [Seq][RegOfVecToMem] Recognize masked memory writes

  #11106·SawyDust1228 opened Sep 11, 2026Contributor·

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  1

• [HandshakeRunner] Fix memref CLI arguments and add missing integer arith ops

  #11104·kevinyuan opened Sep 11, 2026Contributor·

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• Bump LLVM

  #11096·uenoku opened Sep 10, 2026Member·

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  2

• [Calyx] Reject invoke ops passing ref cells to local instances

  #11095·Jimmy-Hu opened Sep 10, 2026·

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  8