The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.

Yosys Open SYnthesis Suite

Compile the Linux kernel for Ubuntu with custom patches and optimizations

Multi-platform nightly builds of open source digital design and verification tools

A SystemC productivity library: https://minres.github.io/SystemC-Components/

Open-source AMBA CHI infrastructures (supporting Issue B, E.b)

A categorized list of C++ resources.

Sail RISC-V model

Packet, where are you? -- eBPF-based Linux kernel networking debugger

Sail architecture definition language

SystemC Reference Implementation

A graphical processor simulator and assembly editor for the RISC-V ISA

RISC-V XV6/Linux SoC, marchID: 0x2b

3-stage RV32IMACZb* processor with debug

SERV - The SErial RISC-V CPU

Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.

Very efficient backup system based on the git packfile format, providing fast incremental saves and global deduplication (among and within files, including virtual machine images). Please post prob…

Hardware Description Languages

SystemC/TLM-2.0 Co-simulation framework

switchable 68K CPU-Core

List of awesome open source hardware tools, generators, and reusable designs

Learning FPGA, yosys, nextpnr, and RISC-V

Reusable Verilog 2005 components for FPGA designs

Repository for the book "Crafting Interpreters"

Verilog PCI express components

Atari ST/STe for MiSTer

Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink

A Verilog HDL model of the MOS 6502 CPU

🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.