The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.

Repository for the book "Crafting Interpreters"

Very efficient backup system based on the git packfile format, providing fast incremental saves and global deduplication (among and within files, including virtual machine images). Please post prob…

A categorized list of C++ resources.

Yosys Open SYnthesis Suite

Packet, where are you? -- eBPF-based Linux kernel networking debugger

Learning FPGA, yosys, nextpnr, and RISC-V

A graphical processor simulator and assembly editor for the RISC-V ISA

List of awesome open source hardware tools, generators, and reusable designs

SERV - The SErial RISC-V CPU

Verilog PCI express components

Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.

Multi-platform nightly builds of open source digital design and verification tools

Hardware Description Languages

RISC-V XV6/Linux SoC, marchID: 0x2b

3-stage RV32IMACZb* processor with debug

Sail architecture definition language

Sail RISC-V model

SystemC Reference Implementation

A Verilog HDL model of the MOS 6502 CPU

Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink

SystemC/TLM-2.0 Co-simulation framework

A SystemC productivity library: https://minres.github.io/SystemC-Components/

switchable 68K CPU-Core

Reusable Verilog 2005 components for FPGA designs

Compile the Linux kernel for Ubuntu with custom patches and optimizations

GDB server to debug CPU simulation waveform traces

Atari ST/STe for MiSTer