Open-source AMBA CHI infrastructures (supporting Issue B, E.b)

Atari ST/STe for MiSTer

MiniMig for TurboChameleon64

switchable 68K CPU-Core

Very efficient backup system based on the git packfile format, providing fast incremental saves and global deduplication (among and within files, including virtual machine images). Please post prob…

GDB server to debug CPU simulation waveform traces

Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink

Verilog PCI express components

Packet, where are you? -- eBPF-based Linux kernel networking debugger

🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.

3-stage RV32IMACZb* processor with debug

Reusable Verilog 2005 components for FPGA designs

Yosys Open SYnthesis Suite

Learning FPGA, yosys, nextpnr, and RISC-V

Multi-platform nightly builds of open source digital design and verification tools

Sail RISC-V model

SERV - The SErial RISC-V CPU

SystemC/TLM-2.0 Co-simulation framework

Sail architecture definition language

SystemC Reference Implementation

A Verilog HDL model of the MOS 6502 CPU

Hardware Description Languages

Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.

Repository for the book "Crafting Interpreters"

A categorized list of C++ resources.

A graphical processor simulator and assembly editor for the RISC-V ISA

Compile the Linux kernel for Ubuntu with custom patches and optimizations