System Daemons for testing UVM on OpenBSD

UP_Counter_4bit_Verification_with_UVM

A lightweight Python-based code generator to produce RAL UVM with coverage

Actividad 08_Visualizacion Grafica

Designed and verified a packet-based Router module as part of hands-on training in RTL design and functional verification using SystemVerilog and UVM.

Low-Power CGRA Design Methodology (WIP)

LC3 Micro_Controller Verification using UVM/UVMF - Constrained Random Verification, Coverage

Digital Watch RTL design with a complete UVM verification environment. Supports timekeeping, time/alarm setting, and stopwatch, achieving 100% functional coverage through constrained-random and directed testing.

Simulaciones

Turning Verilator into a makeshift commercial-ish simulator

Taller de Verificación Funcional usando UVM, para la semana de Ingenería en Electrónica 2024, del Tecnológico de Costa Rica.

"Advanced Peripheral Bus (APB) Verification IP with UVM - Complete testbench with 13 comprehensive tests, GUI simulation, and coverage analysis"

in this repository is there in how to write virtual interface

SystemVerilog ASIC Portfolio: RISC-V SoC Integration, UVM Verification, AI Accelerators & DSP. Full Flow from RTL to GDSII (Cadence).

simulaciones de fisica

Verification project for the High Throughput Advanced X-Bar (HTAX) completed in CSCE 616 (Fall 2025). The work focuses on validating a configurable, protocol-agnostic crossbar supporting scalable ports, virtual channels, and low-latency single- and multi-stage interconnect topologies.

Verification of Memory Using Class Based Environment and UVM Environment

This project uses UVM to verify an SPI Slave connected to internal RAM. It includes multiple agents (active and passive) and integrates assertion-based verification for both SPI and RAM behavior.

CUPTI UVM activity API diagnostic for GB10 / DGX Spark — determines whether CUPTI_ACTIVITY_KIND_UNIFIED_MEMORY_COUNTER is supported at the API level