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uvm

Here are 294 public repositories matching this topic...

witus6969 / RTLC2

Manage and control authorized red team operations with a cross-platform, advanced command and control framework built in Go, C++, and React.

go ui signal-processing verification meter payments sdr smart amr sensors uvm 433mhz c2 command-and-control redteam lnd nodemanager core-lightning

Updated Mar 31, 2026
C++

beztao01 / academia

links a materias de UVM

ingenieria uvm academia iani itiad

Updated Mar 31, 2026
JavaScript

cocotb / cocotb

cocotb: Python-based chip (RTL) verification

python test vhdl verification verilog uvm

Updated Mar 30, 2026
Python

Assaf-Afriat / uvm-template

Reusable UVM verification template — clean, commented, ready to clone for any DUT

template verification systemverilog uvm testbench design-verification

Updated Mar 30, 2026
SystemVerilog

BTA-design-services / tb_lint

TB_LINT - Modular Linting Framework

lint asic linter rtl verilog systemverilog uvm naturaldocs verilator systemverilog-hdl systemverilog-simulation systemverilog-parser verible systemverilog-test-bench systemverilog-language

Updated Mar 30, 2026
Python

sdnellen / open-register-design-tool

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

eda verilog systemverilog uvm registers systemrdl register-descriptions systemrdl-compiler fpga-development asic-design

Updated Mar 30, 2026
Verilog

robtmadsen / low_latency_inference_unit

AI written UVM vs cocotb: a DV comparison using a low-latency NASDAQ ITCH 5.0 inference accelerator (Kintex-7) as DUT. 100% AI-agent built.

uvm cocotb

Updated Mar 30, 2026
HTML

NTP17 / verilator_uvm_verif_framework

Turning Verilator into a makeshift commercial-ish simulator

cpp verilog systemverilog uvm verilator

Updated Mar 29, 2026
HTML

troyguo / dvcon_download

Download proccedings from DVCon

emulation systemverilog uvm dvcon formal verificaiton

Updated Mar 29, 2026
Shell

thebitstreamengineer / REACTION_GAME

Shows the reaction time between LED ON and acknowledgement by user

fpga verilog systemverilog vlsi uvm basys3-fpga

Updated Mar 28, 2026
Tcl

VeriScribe

OYounis / VeriScribe

VeriScribe is a documentation generator tool for SystemVerilog projects.

documentation-tool systemverilog uvm documentation-generator autodoc

Updated Mar 25, 2026
Python

Dragon-Git / uvm_bridge

Bridge systemverilog UVM API with Python by DPI-C, so that Python can be used to write testcases to avoid frequent compilation

python dpi uvm svuvm

Updated Mar 24, 2026
C

SystemRDL / PeakRDL

Control and status register code generator toolchain

asic fpga eda verilog csr command-line-tool systemverilog uvm registers axi amba apb register-descriptions systemrdl-compiler hardware-description-language uvm-register-model

Updated Mar 24, 2026
Python

xver / svdb_gateway

SVDB Gateway : DPI-C library that links SystemVerilog simulations with external SQLite databases for configuration, logging, and verification.

opensource sql sqlite dpi eda sqlite3 systemverilog uvm ipxact uvm-ral-model hardwareverification chipdesign asicdesig designverification

Updated Mar 22, 2026
SystemVerilog

wILLIEWILLYWILLIe / NU_CE387_FPGA-Design

Real-Time Digital Systems Design & Verification with FPGAs (CE387). Featuring SystemVerilog RTL design, UVM methodology, and complete EDA flow using ModelSim, Synplify Pro, and Cadence Innovus.

systemverilog uvm fpga-programming rtl-design

Updated Mar 20, 2026
HTML

AlphaLyrae0 / UVM_RAL_DPI_C_Example

Example of C/C++ register access with name through UVM RAL

verilog systemverilog uvm dpi-c uvm-ral-model uvm-register-model

Updated Mar 15, 2026
SystemVerilog

AlphaLyrae0 / UVM_Simple_Example

Simple UVM example with Altair (Metrics) DSim and Vivado xsim

verilog vivado systemverilog uvm xsim uvm-verification

Updated Mar 15, 2026
SystemVerilog

AlphaLyrae0 / UVM_DPI_Example

Example of DPI-C usage in UVM with Vivado simulator (xsim) and Altair (Metrics) DSim

verilog systemverilog uvm dpi-c uvm-verification

Updated Mar 15, 2026
SystemVerilog

MochiButter / riscv-core

RV64I_Zicsr_Zifencei core

cpu riscv systemverilog uvm

Updated Mar 14, 2026
SystemVerilog

rggen / rggen

Code generation tool for control and status registers

asic fpga vhdl eda rtl verilog csr systemverilog soc uvm ral axi amba apb register-descriptions wishbone-bus uvm-ral-model uvm-register-model wiki-documents

Updated Mar 14, 2026
Ruby

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