vlsi

Functional Bus Description Language compiler front-end written in Go.

A simple asynchronous fifo using a gray counter

Curated SystemVerilog & Verilog interview questions with interview-ready answers — free VLSI study material

Electronics & Communication Engineering Student | Embedded Systems | VLSI | AI & Machine Learning | IoT Enthusiast

Four(4)- bit Arithmetic Logic Unit (ALU) implemented in Verilog with Vivado simulation

An automated RTL-to-Synthesis EDA tool wrapper written in Tcl. Automates multi-module hierarchy checks, SDC constraint generation, Yosys synthesis mapping, and OpenTimer static timing analysis (STA) for the openMSP430 core.

Smart IoT home automation using ESP32 and digital logic

Free browser tools for mature-node MPW readiness, no-GDS RFQ preparation, local GDSII inspection and engineering RFQ cleanup

Advanced VLSI Digital Clock in Verilog (RTL) featuring hardware debouncing, alarm FSM, and a real-time Python/Tkinter GUI dashboard via UART.

Half Adder implementation using Verilog HDL with testbench, simulation and RTL analysis in Xilinx Vivado.

Online GDSII / OASIS / DXF viewer and editor — inspect an IC layout in 2D, in 3D, or as raw records, and check it against design rules, entirely in the browser. Your file is never uploaded. A Blazor WebAssembly PWA, with the parser also on NuGet and as a CLI.

Design and implementation of an optimized 64-bit priority encoder integrated with a cryptographic engine using Verilog HDL.

SystemVerilog program to transmit/receive data in 2 independent channels simultaneously from one UART module.

Verilog implementation of an N-bit comparator with outputs for equal, not equal, greater than, less than, greater than or equal, and less than or equal.

A battle-tested OpenLane guide covering WSL2, Docker, PDK, OpenLane1/OpenLane2 coexistence, GLS, STA, layout tools, and disaster-proof environment management. Read once, never break your OpenLane setup again.

Design and Performance Analysis of a High-Speed Synchronous Binary Counter using Pass Transistor Logic (PTL)

Course project (ESE 3700): 8-bit binary adder — design, simulation, and verification.

Fast VHDL language server written in Rust