A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.
Implementation of Timing Exceptions in RTL design for STA
A parameterizable digital counter implemented as an ASIC, covering the complete RTL-to-GDS design.
Mixed-mode silicon cochlea implementing wavelet processing in 130nm skywater process
Open-source RTL-to-GDS ASIC design flow using Yosys, OpenROAD and SKY130, with scripted implementation, verification and reproducible design stages.
Tiny Tapeout 04 Logic IC. Erics submission of his first real microchip doing basic safety chain control
Design and implementation of a hybrid XOR-based Arbiter Physical Unclonable Function (PUF) on FPGA, followed by ASIC synthesis , enabling lightweight and secure hardware authentication with enhanced uniqueness, entropy, and reliability.
𓁰 PtahCore — open-source FP8 tensor accelerator, RTL→GDSII on open 7nm ASAP7, 100% open toolchain
RTL to GDSII implementation of a Mealy FSM-based ASIC Toll Booth Controller
32-bit RISC-V ASIC physical design featuring a custom standard cell library, bit-sliced datapath routed in Cadence Virtuoso, and automated Cadence Innovus implementation.
8-bit counter RTL-to-GDSII physical design using OpenROAD-flow-scripts and Nangate45.
Tiny Tapeout 5 - WS2812B LED strip driver
High-Level Synthesis project for latency optimisation under area constraints
Projeto introdutório de síntese lógica de uma porta AND em SystemVerilog utilizando o Synopsys Design Compiler com a biblioteca SAED32.
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