Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
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May 10, 2024 - SystemVerilog
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apb
Here are 23 public repositories matching this topic...
Verification IP for AMBA APB Protocol
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Nov 7, 2023 - SystemVerilog
APB master and slave developed in RTL.
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Oct 25, 2025 - SystemVerilog
To design test bench of the APB protocol
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Dec 30, 2020 - SystemVerilog
Common SystemVerilog RTL modules for RgGen
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Dec 23, 2025 - SystemVerilog
APB verification using UVM
verification systemverilog apb systemverilog-test-bench apb-verification apb-verification-using-uvm apb-systemverilog
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Aug 21, 2023 - SystemVerilog
This repo contains a collection of Verilog+System Verilog+RTL+UVM+Protocols Projects
protocol verification eda rtl verilog systemverilog alu vlsi modelsim uvm verilog-hdl axi apb ahb verilog-project vlsi-design design-verification vlsi-project axi-lite system-verilog-testbench
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Sep 13, 2025 - SystemVerilog
APB verification based on Universal verification Method
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Mar 21, 2024 - SystemVerilog
GCD calculator with APB Slave interface.
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Jul 12, 2024 - SystemVerilog
UVM-based functional verification of an APB-based UART Master Core RTL. Includes multi-agent environment, assertions, coverage collection, and multiple test scenarios (full/half duplex, parity, framing, timeout errors) achieving 100% functional coverage and protocol compliance.
fpga eda uart systemverilog vlsi uvm testbench digital-design serial-communication apb functional-verification hardware-verification rtl-design rtl-verification uvm-environment
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Nov 1, 2025 - SystemVerilog
design-and-verification-of-MCDF-phase3
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Nov 17, 2021 - SystemVerilog
This is a bus functional model of Advanced Peripheral Bus.
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Jan 8, 2022 - SystemVerilog
Basic APB-compatible module designed for use with Verilator, but should work with any DPI-C compatible simulator.
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Sep 15, 2022 - SystemVerilog
This project implements an Advanced Peripheral Bus (APB) Master and Slave in SystemVerilog. The APB Master initiates read/write transactions, while the APB Slave responds to these transactions and handles memory access. A dedicated verification environment is provided for each part of the design, including testbenches for the APB Master and Slave.
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Feb 3, 2025 - SystemVerilog
Knowledge hub for digital interfaces
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Nov 13, 2025 - SystemVerilog
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May 14, 2024 - SystemVerilog
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