brent-kung

This script generates and analyzes prefix tree adders.

Implementation of a histogram equalization program using CUDA. Histogram equalization is a technique for adjusting image intensities to enhance contrast.

Performed a comparative study of Parallel Prefix Adders using Verilog HDL on Zynq-7000 APSoC (PL) from XIlinx. Circuits are simulated, synthesized and implemented using Vivado Design Suite.

Gate level implementation of Kogge-Stone and Brent-Kung adders

VLSI Design - Autumn Semester 2022 - Indian Institute of Technology Bombay

An implementation deepdive of scan algorithms in CUDA C++

Parameterizable Adders (Verilog)

A complete single-cycle RISC processor implementation in Verilog featuring an optimized ALU with advanced arithmetic algorithms

Parametric structural adders and multipliers in SystemVerilog: unsigned, signed (Baugh-Wooley and radix-4 Booth) and floating point (FP8 e4m3/e5m2, bf16, fp16), verified exhaustively and placed and routed on sky130 (41-design area-delay sweep)