Python AES

Aspycot: A Spike and Python CO-Simulation Testbench for hardware monitoring IPs

Integration test between Verilog and C++ using VPI

Cosimulator for the Violet core: https://github.com/losfair/Violet

coherence integrates evolutionary computation and co-simulation for the systematic design of protocols for cell culture and biofabrication.

GTKWave Decoders for RISCV

CoSys MAP 2020: Integrating Physical and Virtual Objects in a Simulation Environment

AES-128 co-simulation between SystemVerilog, C DPI, and Python for hardware verification.

GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.

Enables the co-simulation between PSS/E and Matlab/Simulink

Connect to your VHDL simulation via JTAG! GDB <-TCP-> OpenOCD <-remote bitbang-> cosim_jtag <-VHPI or FLI-> VHDL simulator.

Interfacing VHDL and foreign languages with VUnit

USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL

Set of utilities to export/import FMUs out of existing C++ code

High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model

Cosimulation for the Rapid Open Hardware Development (ROHD) framework with other simulators

Tests to evaluate the support of VHDL 2008 and VHDL 2019 features

Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a logic simulation. and drive a memory mapped bus