"Low power" digital standard cells for SKY130 provided by SkyWater.
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Apr 23, 2021 - Verilog
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sky130
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"Medium speed" digital standard cells for SKY130 provided by SkyWater.
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Apr 23, 2021 - Verilog
"Low speed" digital standard cells for SKY130 provided by SkyWater.
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Apr 23, 2021 - Verilog
"High voltage" digital standard cells for SKY130 provided by SkyWater.
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Apr 23, 2021 - Verilog
"High speed" digital standard cells for SKY130 provided by SkyWater.
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Apr 23, 2021 - Verilog
"High density, low leakage" digital standard cells for SKY130 provided by SkyWater.
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Apr 23, 2021 - Verilog
Mixed Signal Circuit Design and Simulation Marathon under very Good category Article: https://www.linkedin.com/pulse/mixed-signal-simulation-marathon-using-esim-sky130-kannan-moudgalya/?trackingId=PLrgw35VThqQ5QB
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Oct 8, 2022 - Verilog
"High density" digital standard cells for SKY130 provided by SkyWater.
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Feb 22, 2023 - Verilog
Fully-differential asynchronous non-binary 12-bit SAR-ADC
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Jun 13, 2023 - Verilog
Anton's "Simple Multiply" submission for Tiny Tapeout 3 (TT03)
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Jan 9, 2024 - Verilog
Implementation of a Ring Oscillator-based Physically Unclonable Function (PUF) in Sky130, with 8 bits of Challenge-Response Pairs (CRP)
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Jun 12, 2024 - Verilog
8 bit RISC Processor for SKY 130nm process
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Jun 17, 2024 - Verilog
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