sky130

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Here are 37 public repositories matching this topic...

b-etz / tt08-morse-keyer

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CW iambic keyer with WPM control, radio passthrough, and 7-segment display output

morse-code amateur-radio cw-keyer sky130 tiny-tapeout

Updated Jul 14, 2025
Verilog

algofoogle / anton1-tt03

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Anton's "Simple Multiply" submission for Tiny Tapeout 3 (TT03)

asic verilog hdl sky130 open-source-silicon

Updated Jan 9, 2024
Verilog

Samizo-AITL / vi-control-asic-sky130

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Educational and practical V–I control ASIC using PID + FSM on SKY130 with OpenLane

education control asic fsm pid eda rtl verilog fixed-point pwm vlsi hardware-design openlane sky130 industrial-control digital-asic

Updated Jan 21, 2026
Verilog

Junde-Lai / Project-Lobster-TPU

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A 4x4 Systolic Array TPU core co-created with Generative AI, featuring RTL to GDSII implementation on Sky130 process.

verilog openlane sky130 ai-accelerator

Updated Mar 20, 2026
Verilog

Shreyasimum / custom-full-adder-rtl2gds

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End-to-end Digital VLSI project demonstrating a Full Adder from RTL to GDS using Yosys and OpenROAD, extended with a custom CMOS Full Adder standard cell and system-level evaluation.

asic vlsi yosys cmos digital-design physical-design openroad standard-cell sky130 rtl-to-gds

Updated Jan 6, 2026
Verilog

algofoogle / tt07-raybox-zero

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TT07 resub of tt04-raybox-zero "3D" VGA ray caster demo (like Wolf3D)

game asic fpga gpu graphics retro verilog raycasting vga 3d ray-casting vga-controller sky130 tinytapeout tiny-tapeout tt07

Updated Apr 27, 2025
Verilog

vyges / vyges-edge-sensor-soc

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Vyges Edge Sensor SoC — Hardware-accelerated vibration monitoring on Sky130A. ChipFoundry Reference Application Design Contest entry.

asic fft soc risc-v caravel openlane sky130 vibration-monitoring chipfoundry

Updated Mar 24, 2026
Verilog

fguzman82 / upb_natalius_soc

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8 bit RISC Processor for SKY 130nm process

processor-architecture verilog risc efabless sky130

Updated Jun 17, 2024
Verilog

Tavakalmastan / ALU16-PPA-Optimization-OpenLane

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RTL-to-GDSII implementation of a 16-bit ALU with PPA optimization using OpenLane (Sky130)

asic ppa vlsi sta openroad openlane sky130 backend-design physcial-design

Updated Feb 26, 2026
Verilog

Mummanajagadeesh / fir-accel-caravel-soc

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Mixed-signal FIR accelerator SoC on Caravel/Sky130A — CIC decimator, 8-tap programmable FIR filter, PWM DAC, Wishbone CSR

asic dsp rtl verilog vlsi caravel openlane sky130

Updated Mar 21, 2026
Verilog

ShekharShwetank / RISC-V_Reference_SoC_Tapeout_Program_Phase_2

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RISC-V Reference SoC Design and Tapeout Program Phase 2 personal documentation

asic synopsys risc-v caravel asic-design sky130 system-on-chip-design scl180nm

Updated Feb 19, 2026
Verilog

VLSI-Shubh / NoCRouter-RTL2GDSII

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A complete 1×3 NoC router implemented from RTL to GDSII using the Sky130A PDK. Includes full functional verification, synthesis (Yosys), and physical design using OpenLane/OpenROAD, culminating in a signoff-clean GDS layout.

router network-on-chip soc-design rtl2gds sky130 chip-design