module lcd_4bit_controller(
    input wire clk,
    input wire resetn,
    input wire enable,          // enable module
    input wire start,           // start transaction (từ AXI)
    input wire rs,              // RS = 0: command, 1: data (từ AXI)
    input wire [7:0] data_in,   // dữ liệu 8-bit (từ AXI)
    output reg busy,            // busy flag
    output reg lcd_rs,
    output reg lcd_rw,
    output reg lcd_en,
    output reg [3:0] lcd_d  
);

// FSM states
localparam [1:0]    IDLE    = 2'b00,
                    INIT    = 2'b01,
                    SEND    = 2'b10;

// Users to add ports here
output wire lcd_rs,
output wire lcd_rw,
output wire lcd_en,
output wire [3:0] lcd_d,
// User ports ends

// Add user logic here
wire start_w;
wire rs_w;
wire [7:0] data_in_w;
wire enable_w;
wire busy_w;

lcd_4bit_controller u_lcd (
    .clk      (s00_axi_aclk),
    .resetn   (s00_axi_aresetn),
    .enable   (enable_w),
    .start    (start_w),
    .rs       (rs_w),
    .data_in  (data_in_w),
    .busy     (busy_w),
    .lcd_rs   (lcd_rs),
    .lcd_rw   (lcd_rw),
    .lcd_en   (lcd_en),
    .lcd_d    (lcd_d)
);
// User logic ends

// Instantiation of Axi Bus Interface S00_AXI
  ...
		.S_AXI_RVALID(s00_axi_rvalid),
		.S_AXI_RREADY(s00_axi_rready),

		.lcd_start		(start_w),
		.lcd_rs			(rs_w),
		.lcd_data_out	(data_in_w),
		.lcd_enable     (enable_w),
		.lcd_busy		(busy_w)
);
endmodule

// Users to add ports here
output wire lcd_start,
output wire lcd_rs,
output wire [7:0] lcd_data_out,
output wire lcd_enable,   // chip select cho lcd_controller
input  wire lcd_busy,
// User ports ends

// Add user logic here

		// Busy flag mapped into CONTROL readback bit7
		// Final CONTROL register readback = slv_reg0 but with bit7 replaced by lcd_busy
		
		wire [31:0] slv_reg0_with_busy;
		assign slv_reg0_with_busy = { slv_reg0[31:8], lcd_busy, slv_reg0[6:0] };

		// Override AXI read data for CONTROL register (address 0x00)
		assign S_AXI_RDATA =
			(axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h0) ? slv_reg0_with_busy :
			(axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h1) ? slv_reg1 :
			(axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h2) ? slv_reg2 :
			(axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h3) ? slv_reg3 : 32'd0;
 
		//--------------------------------------------------------------
		// USER LOGIC
		//--------------------------------------------------------------

		// output registers
		reg       lcd_rs_reg;
		reg [7:0] lcd_data_reg;
		reg       lcd_start_reg;

		assign lcd_rs       = lcd_rs_reg;
		assign lcd_data_out = lcd_data_reg;
		assign lcd_start    = lcd_start_reg;

		// chip select từ CONTROL bit0
		assign lcd_enable   = slv_reg0[0];

		// -----------------------------------------------------
		// thực hiện gửi LCD sau 1 chu kỳ ghi
		// -----------------------------------------------------
		reg last_wvalid;
		reg [1:0] wr_addr_latched;

		// detect write finish (template Vivado thường lệch AW/W)
		wire write_pulse = (S_AXI_WVALID && !last_wvalid);

		always @(posedge S_AXI_ACLK) begin
			last_wvalid <= S_AXI_WVALID;

			if (!S_AXI_ARESETN)
				wr_addr_latched <= 0;
			else if (write_pulse) begin
				wr_addr_latched <= 
					(S_AXI_AWVALID) ?
						S_AXI_AWADDR[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] :
						axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB];
			end
		end

		//------------------------------------------------------------
		// MAIN LOGIC - GỬI LỆNH/DATA SAU KHI REG ĐÃ ỔN ĐỊNH
		//------------------------------------------------------------
		always @(posedge S_AXI_ACLK) begin
			if (!S_AXI_ARESETN) begin
				lcd_rs_reg    <= 0;
				lcd_data_reg  <= 0;
				lcd_start_reg <= 0;
			end else begin
				lcd_start_reg <= 0;   // mặc định

				if (write_pulse && !lcd_busy) begin
					case (wr_addr_latched)

						//------------------------------------------------
						// WRITE CONTROL
						//------------------------------------------------
						2'h0: begin
							lcd_rs_reg <= 0;

							if (slv_reg0[2])        // CLEAR
								lcd_data_reg <= 8'h01;
							else if (slv_reg0[3])   // HOME
								lcd_data_reg <= 8'h80;
							else if (slv_reg0[1])   // LINE2
								lcd_data_reg <= 8'hC0;
							else                    // LINE1
								lcd_data_reg <= 8'h80;

							lcd_start_reg <= 1;
						end

						//------------------------------------------------
						// WRITE DATA
						//------------------------------------------------
						2'h1: begin
							lcd_rs_reg    <= 1;
							lcd_data_reg  <= slv_reg1[7:0];
							lcd_start_reg <= 1;
						end

					endcase
				end
			end
		end

// User logic ends

#define LCD_BASE_ADDR XPAR_MYIP_AXI_LCD_0_BASEADDR

/* Definitions for peripheral MYIP_AXI_LCD_0 */
#define XPAR_MYIP_AXI_LCD_0_BASEADDR 0xa0000000
#define XPAR_MYIP_AXI_LCD_0_HIGHADDR 0xa000ffff