GPT4All: Run Local LLMs on Any Device. Open-source and available for commercial use.

GoogleTest - Google Testing and Mocking Framework

Yosys Open SYnthesis Suite

SystemVerilog compiler and language services

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

SystemRDL 2.0 language compiler front-end

A slimline C++ class for parsing command-line arguments, with an interface similar to python's class of the same name

Kactus2 is a graphical EDA tool based on the IP-XACT standard.

RISC-V RV64GC emulator designed for RTL co-simulation

Virtual Platform for NVDLA

A generic C++ API for SMT solving. It provides abstract classes which can be implemented by different SMT solvers.

Pono: A flexible and extensible SMT-based model checker

The HW-CBMC and EBMC Model Checkers for Verilog

A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.

Mutation Cover with Yosys (MCY)

A Modeling and Verification Platform for SoCs using ILAs

Hardware generator debugger

⚔️ Debuggable hardware generator

基于 ChatGPT 的跨平台桌面端翻译软件 - A cross-platform desktop translation software based on ChatGPT.

Hardware Verification library for C++, SystemC and SystemVerilog

make your verilog DUT test more smart

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format …

CMurphi mirror: http://mclab.di.uniroma1.it/site/index.php/software/18-cmurphi

Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python

Run Python functions in System-Verilog with supporting the interplay between numpy and svOpenArrayHandle. Also optimize the runtime performance.

Heterogeneous implementation of MPI with FPGA support

SystemC UVM environment generator for PyGears components. RTL simulated with Verilator

an easy bus verification example based on UVM/SV framework

Verilator Testbench Environment

Simple console/file logging library used across many of my projects.