Lists (6)
Starred repositories
Synesthesia - Experiments Wth Light & Sound on the DE1
Framework to perform DUT vs ISS (Whisper) lockstep architectural checks
Public repository for PySysC, (From SC Common Practices Subgroup)
Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verification of verilog systems.
Run Python functions in System-Verilog with supporting the interplay between numpy and svOpenArrayHandle. Also optimize the runtime performance.
Yet another query language. Mirror of code maintained at opendev.org.
A framework for building application-level debuggers for bleeding-edge hardware systems.
A CI/CD Environment for Processor Simulation and Verification.
Convert PDF with grammar of IEEE1076-2008 and IEEE1800-2017 to ANTLR4 grammar
VeriPy is a python based Verilog/Systemverilog automation tool. It automates ports/wire/reg/logic declarations, sub-module Instantiation, embedded python, IO spec flow, memory wrapper generation, v…
Collection of some challenging and tricky constraints
A formatter to make your CMake code the real treasure
A query / expression language for performing computations on JSON-like structures. Built for easy embedding in applications.
An interpreted relational query language that compiles to SQL.
Lark is a parsing toolkit for Python, built with a focus on ergonomics, performance and modularity.
Library to convert natural language utterance into a structured domain specific language
List of awesome open source hardware tools, generators, and reusable designs
Python as DSL for writing PlantUML sequence diagrams
Your Gateway to Embedded Software Development Excellence 👽
Generic automation framework for acceptance testing and RPA
CocoAlma is an execution-aware tool for formal verification of masked implementations