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written in VHDL
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VUnit is a unit testing framework for VHDL/SystemVerilog
Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a logic simulation. and drive a memory mapped bus
Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
Trying to verify Verilog/VHDL designs with formal methods and tools
The FPGA design for MICS' Hybrid DFR System