TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS245E −MARCH 2000 − REVISED APRIL 2010

D Maximum Throughput . . . 140/200 KSPS − TLV2542: Dual Channels With

D Built-In Conversion Clock Autosweep
− TLV2545: Single Channel With
D INL/DNL: ±1 LSB Max, SINAD: 72 dB,
Pseudo-Differential Input
SFDR: 85 dB, fi = 20 kHz
D SPI/DSP-Compatible Serial Interface
D Low Power With Autopower Down
− Operating Current: 1 mA at 2.7 V, 1.5 mA
D Single Supply: 2.7 Vdc to 5.5 Vdc at 5 V
D Rail-to-Rail Analog Input With 500 kHz BW Autopower Down: 2 μA at 2.7 V, 5 μA
D Three Options Available: at 5 V
− TLV2541: Single Channel Input D Small 8-Pin MSOP and SOIC Packages

TOP VIEW TOP VIEW TOP VIEW

TLV2541 TLV2542 TLV2545

CS 1 8 SDO CS 1 8 SDO CS 1 8 SDO

VREF 2 7 FS VREF 2 7 SCLK VREF 2 7 SCLK
GND 3 6 VDD GND 3 6 VDD GND 3 6 VDD
AIN 4 5 SCLK AIN0 4 5 AIN1 AIN(+) 4 5 AIN(−)

description
The TLV2541, TLV2542, and TLV2545 are a family of high performance, 12-bit, low power, miniature, CMOS
analog-to-digital converters (ADC). The TLV254x family operates from a single 2.7-V to 5.5-V supply. Devices
are available with single, dual, or single pseudo-differential inputs. Each device has a chip select (CS), serial
clock (SCLK), and serial data output (SDO) that provides a direct 3-wire interface to the serial port of most
popular host microprocessors (SPI interface). When interfaced with a TMS320t DSP, a frame sync signal (FS)
can be used to indicate the start of a serial data frame on CS for all devices or FS for the TLV2541.
TLV2541, TLV2542, and TLV2545 are designed to operate with very low power consumption. The power saving
feature is further enhanced with an autopower-down mode. This product family features a high-speed serial link
to modern host processors with SCLK up to 20 MHz. The maximum SCLK frequency is dependent upon the
mode of operation (see Table 1). The TLV254x family uses the built-in oscillator as the conversion clock,
providing a 3.5-μs conversion time.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA 8-MSOP 8-SOIC
(DGK) (D)
TLV2541CDGK (AGZ)
0°C
0 70°C
C to 70 C TLV2542CDGK (AHB)
TLV2545CDGK (AHD)
TLV2541IDGK (AHA) TLV2541ID
−40°C
40 C to 85°C
85 C TLV2542IDGK (AHC) TLV2542ID
TLV2545IDGK (AHE) TLV2545ID

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TMS320 is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Copyright © 2000 − 2003, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 1
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
TLV2541, TLV2542, TLV2545
2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS245E −MARCH 2000 − REVISED APRIL 2010

functional block diagram

TLV2541 TLV2542

VDD VDD

VREF VREF
AIN0
Mux
LOW POWER AIN1
AIN S/H 12-BIT SDO
SAR ADC
S/H LOW POWER SDO
SAR ADC
OSC
Conversion
Clock
OSC
Conversion
SCLK Clock
CONTROL
CS
LOGIC SCLK CONTROL
FS
CS LOGIC

GND GND
TLV2545
VDD

VREF

AIN (+) LOW POWER

S/H 12-BIT SDO
AIN (−) SAR ADC

OSC Conversion
Clock

SCLK CONTROL
CS LOGIC

GND

2 •
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
 TLV2541, TLV2542, TLV2545
2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS245E −MARCH 2000 − REVISED APRIL 2010

Terminal Functions

TLV2541
TERMINAL
I/O DESCRIPTION
NAME NO.
AIN 4 I Analog input channel
CS 1 I Chip select. A high-to-low transition on the CS input removes SDO from 3-state within a maximum setup time.
CS can be used as the FS pin when a dedicated DSP serial port is used.
FS 7 I DSP frame sync input. Indication of the start of a serial data frame. Tie this terminal to VDD if not used.
GND 3 I Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND.
SCLK 5 I Output serial clock. This terminal receives the serial SCLK from the host processor.
SDO 8 O The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state until CS falling edge
or FS rising edge, whichever occurs first. The output format is MSB first.
When FS is not used (FS = 1 at the falling edge of CS): The MSB is presented to the SDO pin after CS falling edge
and output data is valid on the first falling edge of SCLK.
When CS and FS are both used (FS = 0 at the falling edge of CS): The MSB is presented to the SDO pin after the
falling edge of CS. When CS is tied/held low, the MSB is presented on SDO after the rising FS. Output data is valid
on the first falling edge of SCLK. (This is typically used with an active FS from a DSP using a dedicated serial port.)
VDD 6 I Positive supply voltage
VREF 2 I External reference input

TLV2542/45
TERMINAL
I/O DESCRIPTION
NAME NO.
AIN0 /AIN(+) 4 I Analog input channel 0 for TLV2542—Positive input for TLV2545.
AIN1/AIN (−) 5 I Analog input channel 1 for TLV2542—Inverted input for TLV2545.
CS 1 I Chip select. A high-to-low transition on CS removes SDO from 3-state within a maximum delay time. This pin can
be connected to the frame sync of a DSP using a dedicated serial port.
GND 3 I Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND.
SCLK 7 I Output serial clock. This terminal receives the serial SCLK from the host processor.
SDO 8 O The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state when CS is high
and presents output data after the CS falling edge until the LSB is presented. The output format is MSB first. SDO
returns to the Hi-Z state after the 16th SCLK. Output data is valid on the falling SCLK edge.
VDD 6 I Positive supply voltage
VREF 2 I External reference input

detailed description
The TLV2541, TLV2542, and TLV2545 are successive approximation (SAR) ADCs utilizing a charge
redistribution DAC. Figure 1 shows a simplified version of the ADC.
The sampling capacitor acquires the signal on AIN during the sampling period. When the conversion process
starts, the SAR control logic and charge redistribution DAC are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator into a balanced condition. When the comparator is
balanced, the conversion is complete and the ADC output code is generated.

•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 3
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
TLV2541, TLV2542, TLV2545
2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS245E −MARCH 2000 − REVISED APRIL 2010

detailed description (continued)

Charge
Redistribution
DAC

AIN _
Control
Logic ADC Code
+

GND/AIN(−)

Figure 1. Simplified SAR Circuit

serial interface
OUTPUT DATA FORMAT
MSB LSB
D15−D4 D3−D0
Conversion result (OD11−OD0) Don’t care

The output data format is binary (unipolar straight binary).

binary
Zero-scale code = 000h, Vcode = GND
Full-scale code = FFFh, Vcode = VREF − 1 LSB
pseudo-differential inputs
The TLV2545 operates in pseudo-differential mode. The inverted input is available on pin 5. It can have a
maximum input ripple of ±0.2 V. This is normally used for ground noise rejection.

control and timing

start of the cycle
Each cycle may be started by either CS, FS, or a combination of both. The internal state machine requires one
SCLK high-to-low transition to determine the state of these control signals so internal blocks can be powered
up in an active cycle. Special care to SPI mode is necessary. Make sure there is at least one SCLK whenever
CS (pin 1) is high to ensure proper operation.
TLV2541
D Control via CS ( FS = 1 at the falling edge of CS)—The falling edge of CS is the start of the cycle. The MSB
should be read on the first falling SCLK edge after CS is low. Output data changes on the rising edge of
SCLK. This is typically used for a microcontroller with an SPI interface, although it can also be used for a
DSP. The microcontroller SPI interface should be programmed for CPOL = 0 (serial clock referenced to
ground) and CPHA = 1 (data is valid on the falling edge of the serial clock). At least one falling edge transition
on SCLK is needed whenever CS is brought high.
D Control via FS (CS is tied/held low)—The MSB is presented after the rising edge of FS. The falling edge
of FS is the start of the cycle. The MSB should be read on the first falling edge of SCLK after FS is low. This
is the typical configuration when the ADC is the only device on the DSP serial port.

4 •
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
 TLV2541, TLV2542, TLV2545
2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS245E −MARCH 2000 − REVISED APRIL 2010

control and timing (continued)

D Control via both CS and FS—The MSB is presented after the falling edge of CS. The falling edge of FS is
the start of the sampling cycle. The MSB should be read on the first falling SCLK edge after FS is low. Output
data changes on the rising edge of SCLK. This configuration is typically used for multiple devices connected
to a TMS320 DSP.
TLV2542/5
All control is provided using CS (pin 1) on the TLV2542 and TLV2545. The cycle is started on the falling edge
transition provided by either a CS signal from an SPI microcontroller or FS signal from a TMS320 DSP. Timing
is similar to the TLV2541, with control via CS only.

TLV2542 channel MUX reset cycle

The TLV2542 uses CS to reset the analog input multiplexer. A short active CS cycle (4 to 7 SCLKs) resets the
MUX to AIN0. When the CS cycle time is greater than 7 SCLKs in duration, as in the case for a complete
conversion cycle (CS is low for 16 SCLKs plus maximum conversion time), the MUX toggles to the next channel
(see Figure 4 for timing). One dummy conversion cycle is recommended after power up before attempting to
reset the MUX.

sampling
The converter sample time is 12 SCLKs in duration, beginning on the fifth SCLK received after the converter
has received a high-to-low CS transition (or a high-to-low FS transition for the TLV2541).

conversion
The TLV2541, TLV2542, and TLV2545 complete conversions in the following manner. The conversion is started
after the 16th SCLK falling edge and takes 3.5 μs to complete. Enough time (for conversion) should be allowed
before a rising CS or FS edge so that no conversion is terminated prematurely.
TLV2542 input channel selection is toggled on each rising CS edge. The MUX channel can be reset to AIN0
via CS as described in the earlier section and in Figure 4. The input is sampled for 12 SCLKs, converted, and
the result is presented on SDO during the next cycle. Care should also be taken to allow enough time between
samples to avoid prematurely terminating the cycle, which occurs on a rising CS transition if the conversion is
not complete.
The SDO data presented during a cycle is the result of the conversion of the sample taken during the previous
cycle.

timing diagrams/conversion cycles

1 2 3 4 5 6 7 12 13 14 15 16 1

SCLK

CS

FS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
t(sample) t(powerdown)
tc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SDO OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD0

Figure 2. TLV2541 Timing: Control via CS (FS = 1)

•
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POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
TLV2541, TLV2542, TLV2545
2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS245E −MARCH 2000 − REVISED APRIL 2010

timing diagrams/conversion cycles (continued)

1 2 3 4 5 6 12 13 14 15 16 1

SCLK

CS

FS

t(sample)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tc
t(powerdown)

SDO OD11 OD10 OD9 OD8 OD7 OD6 OD0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Figure 3. TLV2541 Timing: Control via CS and FS or FS Only
1 2 3 4 5 1 4 12 16 1 4 12 16

SCLK

>8 SCLKs, MUX Toggles to AIN1

<8 SCLKs, MUX
CS Resets to AIN0

t(powerdown)
t(sample) t(sample)

SDO
ÎÎÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎÎÎÎ
tc
AIN0 Result
OD11 OD0
ÎÎÎ
ÎÎÎ
tc

Figure 4. TLV2542 Reset Timing

1 2 3 4 5 6 7 12 13 14 15 16 1

SCLK

CS

ÎÎÎÎÎÎ
t(sample) t(powerdown)
tc
SDO OD11 OD10 OD9 OD8 OD7 OD6 OD5

ÎÎÎÎÎÎ
OD0 OD11 OD10 OD9

Figure 5. TLV2542 and TLV2545 Timing

using CS as the FS input

When interfacing the TLV2541 with the TMS320 DSP, the FSR signal from the DSP may be connected to the
CS input if this is the only device on the serial port. This saves one output terminal from the DSP. (Output data
changes on the falling edge of SCLK. This is the default configuration for the TLV2542 and TLV2545.)

6 •
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
 TLV2541, TLV2542, TLV2545
2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS245E −MARCH 2000 − REVISED APRIL 2010

using CS as the FS input (continued)

SCLK and conversion speed
The input frequency of SCLK can range from 100 kHz to 20 MHz maximum. The ADC conversion uses a
separate internal oscillator with a minimum frequency of 4 MHz. The conversion cycle takes 14 internal oscillator
clocks to complete. This leads to a 3.5-μs conversion time. For a 20-MHz SCLK, the minimum total cycle time
is given by: 16x(1/20M)+14x(1/4M)+one SCLK = 4.35 μs. An additional SCLK is added to account for the
required CS and/or FS high time. These times specify the minimum cycle time for an active CS or FS signal.
If violated, the conversion terminates, invalidating the next data output cycle. Table 1 gives the maximum SCLK
frequency for a given supply voltage and operational mode.
control via pin 1 (CS, SPI interface)
All devices are compatible with this mode operation. A falling CS initiates the cycle (for TLV2541, the FS input
is tied to VDD). CS remains low for the entire cycle time (sample+convert+one SCLK) and can then be released.
NOTE:
IMPORTANT: A single SCLK is required whenever CS is high.
control via pin 1 (CS, DSP interface)
All devices are compatible with this mode of operation. The FS signal from a DSP is connected directly to the
CS input of the ADC. A falling edge on the CS input initiates the cycle. (For the TLV2541, the FS input can be
tied to VDD, although better performance can be achieved when using the FS input for control. Refer to the next
section.) The CS input should remain low for the entire cycle time (sample+convert+one SCLK) and can then
be released.
NOTE:
IMPORTANT: A single SCLK is required whenever CS is high. This should be of little consequence,
since SCLK is normally always present when interfacing with a DSP.
control via pin 1 and pin 7 (CS and FS or FS only, DSP interface)
Only the TLV2541 is compatible with this mode of operation. The CS input to the ADC can be controlled via a
general-purpose I/O pin from the DSP. The FS signal from the DSP is connected directly to the FS input of the
ADC. A falling edge on CS, if used, releases the MSB on the SDO output. When CS is not used, the rising FS
edge releases the MSB. The falling edge on the FS input while SCLK is high initiates the cycle. The CS and
FS inputs should remain low for the entire cycle time (sample+convert+one SCLK) and can then be released.
reference voltage
An external reference is applied via VREF. The voltage level applied to this pin establishes the upper limit of the
analog inputs to produce a full-scale reading. The value of VREF and the analog input should not exceed the
positive supply or be less than GND, consistent with the specified absolute maximum ratings. The digital output
is at full scale when the input signal is equal to or higher than VREF and at zero when the input signal is equal
to or lower than GND.
power down and power up
Autopower down is built into these devices in order to reduce power consumption. The actual power savings
depends on the inactive time between cycles and the power supply (loading) decoupling/storage capacitors.
Power-down takes effect immediately after the conversion is complete. This is fast enough to provide some
power savings between cycles with longer than 1 SCLK inactive time. The device power goes down to 5 μA
within 0.5 μs. To achieve the lowest power-down current (deep powerdown) of 1 μA requires 2-ms inactive time
between cycles. The power-down state is initiated at the end of conversion. These devices wake up immediately
at the next falling edge of CS or the rising edge of FS.

•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 7
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
TLV2541, TLV2542, TLV2545
2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS245E −MARCH 2000 − REVISED APRIL 2010

ICC
With 1-μF/0.1-μF Capacitor Between Supply and Ground

VDD = 5 V VDD = 2.7 V 0.5 μS

2 mS
1.5 mA

0.95 mA

5 μA
2 μA

1 μA 1 μA

t(Powerdown) − Powerdown time − S

Table 1. Modes of Operation and Data Throughput

APPROXIMATE
MAX SCLK (MHz) CONVERSION
CONTROL PIN(s)/DEVICE (50/50 duty cycle) THROUGHPUT
(ksps)
VDD = 2.7 V VDD = 4.5 V VDD = 2.7 V VDD = 4.5 V
CS control only (TLV2541 only)
For SPI interface† 10 15 175 200
For DSP interface (Use CS as FS)‡ 5 8 140 175
CS and FS control (TLV2541 only)§
DSP interface 15 20 200 200
† See Figure 29(a).
‡ See Figure 29(b).
§ See Figure 29(c).

absolute maximum ratings over operating free-air temperature (unless otherwise noted)¶
Supply voltage range, GND to VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6.5 V
Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD + 0.3 V
Reference input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD + 0.3 V
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD+ 0.3 V
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C
Operating free-air temperature range, TA: C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
¶ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

8 •
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
 TLV2541, TLV2542, TLV2545
2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS245E −MARCH 2000 − REVISED APRIL 2010

recommended operating conditions

MIN NOM MAX UNIT
Supply voltage, VDD 2.7 3.3 5.5 V
Positive external reference voltage input, VREFP (see Note 1) 2 VDD V
Analog input voltage (see Note 1) 0 VDD V
High level control input voltage, VIH 2.1 V
Low-level control input voltage, VIL 0.6 V
Setup time, CS falling edge before first SCLK falling edge, VDD = REF = 4.5 V 40
ns
tsu(CSL-SCLKL) VDD = REF = 2.7 V 70
Hold time, CS falling edge after SCLK falling edge, th(SCLKL-CSL) 5 ns
Delay time, delay from CS falling edge to FS rising edge, td(CSL-FSH) (TLV2541 only) 0.5 7 SCLKs
Setup time, FS rising edge before SCLK falling edge, tsu(FSH-SCLKL) (TLV2541 only) 0.35 SCLKs
Hold time, FS high after SCLK falling edge, th(SCLKL-FSL) (TLV2541 only) 0.65 SCLKs
Pulse width CS high time, tw(H_CS) 100 ns
Pulse width FS high time, tw(H_FS) (TLV2541 only) 0.75 SCLKs
SCLK cycle time, VDD = 3.6 V to 2.7 V, tc(SCLK) (maximum tolerance of 40/60 duty cycle) 90 10000 ns
SCLK cycle time, VDD = 5.5 V to 4.5 V, tc(SCLK) (maximum tolerance of 40/60 duty cycle) 50 10000 ns
Pulse width low time, tw(L_SCLK) 0.4 0.6 SCLK
Pulse width high time, tw(H_SCLK) 0.4 0.6 SCLK
Hold time, hold from end of conversion to CS high, th(EOC-CSH) (EOC is internal, indicates end of conversion
0.05 μs
time, tc)
Active CS cycle time to reset internal MUX to AIN0, t(reset cycle) (TLV2542 only) 4 7 SCLKs
VDD = REF = 4.5 V, 25-pF load 40
Delay time,
time delay from CS falling edge to SDO valid,
valid td(CSL-SDOV) ns
VDD = REF = 2.7 V, 25-pF load 70
Delay time, delay from FS falling edge to SDO valid, td(FSL-SDOV) VDD = REF = 4.5 V, 25-pF load 1
ns
(TLV2541 only) VDD = REF = 2.7 V, 25-pF load 1
Delay time, delay from SCLK rising edge to SDO valid, VDD = REF = 4.5 V, 25-pF load 11
ns
td(SCLKH-SDOV) VDD = REF = 2.7 V, 25-pF load 21
Delay time, delay from 17th SCLK rising edge to SDO 3-state,
3 state, VDD = REF = 4.5 V, 25-pF load 30
ns
td(SCLK17H-SDOZ) VDD = REF = 2.7 V, 25-pF load 60
Conversion clock = internal
Conversion time, tc 2.1 2.6 3.5 μs
oscillator
Sampling time, t(sample) See Note 2 300 ns
TLV2541/2/5C 0 70
Operating free-air
free air temperature
temperature, TA °C
TLV2541/2/5I −40 85
NOTES: 1. Analog input voltages greater than that applied to VREF convert as all ones (111111111111), while input voltages less than that applied
to GND convert as all zeros(000000000000).
2. Minimal t(sample) is given by 0.9 × 50 pF × (RS + 0.5 kΩ), where RS is the source output impedance.

•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 9
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
TLV2541, TLV2542, TLV2545
2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS245E −MARCH 2000 − REVISED APRIL 2010

electrical characteristics over recommended operating free-air temperature range,

VDD = VREF = 2.7 V to 5.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT
VDD = 5.5 V, IOH = −0.2 mA at 30-pF load 2.4
VOH High level output voltage
High-level V
VDD = 2.7 V, IOH = -20 μA at 30-pF load VDD−0.2
VDD = 5.5 V, IOL = 0.8 mA at 30-pF load 0.4
VOL Low level output voltage
Low-level V
VDD = 2.7 V, IOL = 20 μA at 30-pF load 0.1

Off-state output current VO = VDD 1 2.5

IOZ CS = VDD A
μA
(high-impedance-state) VO = 0 −1 −2.5
IIH High-level input current VI = VDD 0.005 2.5 μA
−0.00
IIL Low-level input current VI = 0 V 2.5 μA
5
VDD = 4.5 V to 5.5 V 1.3 1.5
ICC Operating supply current CS at 0 V mA
VDD = 2.7 V to 3.3 V 0.85 0.95
For all digital inputs,
Autopower-down current 0≤ VI ≤ 0.3 V or VI ≥ VDD− 0.3 V, 5
SCLK = 0, VDD = 4.5 V to 5.5 V, Ext ref μA
t(powerdown) ≥ 0.5 μs
VDD = 2.7 V to 3.3 V, Ext ref 2
ICC(AUTOPWDN)
For all digital inputs,
Deep autopower-down current 0≤ VI ≤ 0.3 V or VI ≥ VDD− 0.3 V, 1
SCLK = 0, VDD = 4.5 V to 5.5 V, Ext ref μA
t(powerdown) ≥ 2 ms
VDD = 2.7 V to 3.3 V 1

Selected analog input channel Selected channel at VDD 1

A
μA
leakage current Selected channel at 0 V −1
Analog inputs 20 45 50
Ci Input capacitance pF
Control Inputs 5 25
VDD = 5.5 V 500
Input on resistance Ω
VDD = 2.7 V 600
Autopower down 0.5 SCLK
† All typical values are at VDD = 5 V, TA = 25°C.

10 •
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
 TLV2541, TLV2542, TLV2545
2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS245E −MARCH 2000 − REVISED APRIL 2010

ac specifications (fi = 20 kHz)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
200 KSPS, VDD = VREF = 5.5 V 70 72
SINAD Signal to noise ratio +distortion
Signal-to-noise dB
150 KSPS, VDD = VREF = 2.7 V 68 71
200 KSPS, VDD = VREF = 5.5 V −84 −80
THD Total harmonic distortion dB
150 KSPS, VDD = VREF = 2.7 V −84 −80
200 KSPS, VDD = VREF = 5.5 V 11.8
ENOB Effective number of bits Bits
150 KSPS, VDD = VREF = 2.7 V 11.6
200 KSPS, VDD = VREF = 5.5 V −84 −80
SFDR Spurious free dynamic range dB
150 KSPS, VDD = VREF = 2.7 V −84 −80
Analog Input
Full-power bandwidth, −3 dB 1 MHz
Full-power bandwidth, −1 dB 500 kHz

external reference specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Reference input voltage VDD = 2.7 V to 5.5 V 2 VDD V
CS = 1, SCLK = 0 100 MΩ
VDD = 5 5V
5.5
CS = 0, SCLK = 20 MHz 20 25 kΩ
Reference input impedance
CS = 1, SCLK = 0 100 MΩ
VDD = 2
2.7
7V
CS = 0, SCLK = 20 MHz 20 25 kΩ
VDD = VREF = 5.5 V, CS = 0, SCLK = 20 MHz 100 400
Reference current μA
VDD = VREF = 2.7 V, CS = 0, SCLK = 20 MHz 50 200
CS = 1, SCLK = 0 5 15
VDD = VREF = 5
5.5
5V
CS = 0, SCLK = 20 MHz 20 45 50
Reference input capacitance pF
CS = 1, SCLK = 0 5 15
VDD = VREF = 2
2.7
7V
CS = 0, SCLK = 20 MHz 20 45 50
VREF Reference voltage VDD = 2.7 V to 5.5 V VDD V

dc specification, VDD = VREF = 2.7 V to 5.5 V, SCLK frequency = 20 MHz at 5 V, 15 MHz at 3 V (unless otherwise
noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INL Integral linearity error (see Note 4) ±0.6 ±1 LSB
DNL Differential linearity error See Note 3 ±0.5 ±1 LSB
TLV2541/42 ±1.5
EO Offset error (see Note 5) See Note 3 LSB
TLV2545 ±2.5
TLV2541/42 ±2
EG Gain error (see Note 5) See Note 3 LSB
TLV2545 ±5
TLV2541/42 ±2
Et Total unadjusted error (see Note 6) See Note 3 LSB
TLV2545 ±5
NOTES: 3. Analog input voltages greater than that applied to VREF convert as all ones (111111111111).
4. Linear error is the maximum deviation from the best straight line through the A/D transfer characteristics.
5. Zero error is the difference between 000000000000 and the converted output for zero input voltage: full-scale error is the difference
between 111111111111 and the converted output for full-scale input voltage.
6. Total unadjusted error comprises linearity, zero, and full-scale errors.

•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 11
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
TLV2541, TLV2542, TLV2545
2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS245E −MARCH 2000 − REVISED APRIL 2010

PARAMETER MEASUREMENT INFORMATION

t(sample)

tw(H_SCLK) tc

VIH 1 2 4 12 16

SCLK

VIL
tw(L_SCLK)
tsu(CSL-SCLKL) t(powerdown)

CS

th(SCLKL-FSL) tw(H_CS)

tsu(FSH-SCLKL) th(EOC-CSH)

td(CSL-FSH)
td(SCLKH-SDOV)

FS

ÎÎÎÎÎ ÎÎÎÎÎ
tw(H_FS) td(SCLK17H-SDOZ)

SDO
ÎÎÎÎÎ td(CSL-SDOV)
OD11 OD8 OD0
ÎÎÎÎÎ
Figure 6. TLV2541 Critical Timing (Control via CS and FS or FS only)

t(sample)
tsu(CSL−SCLKL)
tc

1 2 4 12 16

SCLK

t(powerdown)

CS

ÎÎÎÎÎÎÎ
td(SCLKH-SDOV) td(SCLK17H-SDOZ)

SDO OD11 OD10 OD9 OD0

ÎÎÎÎÎÎÎ th(EOC−CSH)
td(CSL-SDOV)

Figure 7. TLV2541 Critical Timing (Control via CS only, FS = 1)

12 •
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
 TLV2541, TLV2542, TLV2545
2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS245E −MARCH 2000 − REVISED APRIL 2010

PARAMETER MEASUREMENT INFORMATION

t(sample)

tc

1 1 4 12 16

SCLK

t(reset cycle)

CS MUX = AIN0

tw(H_CS)
th(EOC-CSH)
td(SCLKH-SDOV)
td(CSL-SDOV)

SDO ÎÎÎÎ
ÎÎÎÎ
OD11 OD0
ÎÎÎÎÎ
ÎÎÎÎÎ
OD11

td(CSL-SDOV) td(SCLK17H-SDOZ)

Figure 8. TLV2542 Reset Cycle Critical Timing

tw(H_SCLK) t(sample) tc

VIH 1 2 4 12 16

SCLK

VIL
th(SCLKL-CSL) tw(L_SCLK)

t(powerdown)
tsu(CSL-SCLKL)

CS

tw(H_CS)
td(SCLKH-SDOV) th(EOC-CSH)

ÎÎÎÎÎ
td(SCLK17H-SDOZ)

SDO OD11

td(CSL-SDOV)
OD8 OD0

ÎÎÎÎÎ
Figure 9. TLV2542 and TLV2545 Conversion Cycle Critical Timing

•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 13
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
TLV2541, TLV2542, TLV2545
2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS245E −MARCH 2000 − REVISED APRIL 2010

TYPICAL CHARACTERISTICS

INTEGRAL NONLINEARITY INTEGRAL NONLINEARITY

vs vs
FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
0.7 0.6
VDD = REF = 2.7 V VDD = REF = 5.5 V
150 KSPS 200 KSPS
INL − Integral Nonlinearity − LSB

INL − Integral Nonlinearity − LSB

0.65 0.55

0.6 0.5
−40 25 90 −40 25 90
TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C
Figure 10 Figure 11

DIFFERENTIAL NONLINEARITY DIFFERENTIAL NONLINEARITY

vs vs
FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
0.6 0.35
VDD = REF = 2.7 V VDD = REF = 5.5 V
150 KSPS 200 KSPS
DNL − Differential Nonlinearity − LSB
DNL − Differential Nonlinearity − LSB

0.5

0.4

0.3 0.3

0.2

0.1

0 0.25
−40 25 90 −40 25 90
TA − Free-Air Temperature − °C TA − Free-air Temperature − °C

Figure 12 Figure 13

14 •
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
 TLV2541, TLV2542, TLV2545
2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS245E −MARCH 2000 − REVISED APRIL 2010

TYPICAL CHARACTERISTICS

OFFSET ERROR GAIN ERROR

vs vs
FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
0.5 0.9
VDD = REF = 2.7 V VDD = REF = 5.5 V
150 KSPS 200 KSPS
0.4
Offset Error − LSB

Gain Error − LSB

0.3

0.85

0.2

0.1

0 0.8
−40 25 90 −40 25 90
TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C

Figure 14 Figure 15
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
1.5
VDD = REF = 5.5 V
200 KSPS
Supply Current − mA

1.4

1.3

1.2
−40 25 90
TA − Free-Air Temperature − °C

Figure 16

•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 15
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
TLV2541, TLV2542, TLV2545
2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS245E −MARCH 2000 − REVISED APRIL 2010

TYPICAL CHARACTERISTICS
INTEGRAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODES
1
INL − Integral Nonlinearity − LSB

VDD = REF = 2.7 V

150 KSPS
0.5

−0.5

−1
1 4095
Digital Output Codes

Figure 17

DIFFERENTIAL NONLINEARITY ERROR

vs
DIGITAL OUTPUT CODES
DNL − Differential Nonlinearity − LSB

1
VDD = REF = 2.7 V
150 KSPS
0.5

−0.5

−1
1 4095
Digital Output Codes

Figure 18

16 •
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
 TLV2541, TLV2542, TLV2545
2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS245E −MARCH 2000 − REVISED APRIL 2010

TYPICAL CHARACTERISTICS
INTEGRAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODES
1
INL − Integral Nonlinearity − LSB

VDD = REF = 5.5 V

200 KSPS
0.5

−0.5

−1
1 4095
Digital Output Codes

Figure 19

DIFFERENTIAL NONLINEARITY ERROR

vs
DIGITAL OUTPUT CODES
DNL − Differential Nonlinearity − LSB

1
VDD = REF = 5.5 V
200 KSPS
0.5

−0.5

−1
1 4095
Digital Output Codes

Figure 20

•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 17
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
TLV2541, TLV2542, TLV2545
2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS245E −MARCH 2000 − REVISED APRIL 2010

TYPICAL CHARACTERISTICS
2048 POINTS FAST FOURIER TRANSFORM (FFT)
0
VDD = REF = 2.7 V
−20 150 KSPS
fi = 20 kHz
−40
Magnitude − dB

−60

−80

−100

−120
−140
0 20 40 60 80 100
f − Input Frequency − KHz

Figure 21

2048 POINTS FAST FOURIER TRANSFORM (FFT)

0
VDD = REF = 5.5 V
−20 200 KSPS
fi = 20 kHz
−40
Magnitude − dB

−60

−80

−100

−120
−140
0 20 40 60 80 100
f − Input Frequency − KHz

Figure 22

18 •
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
 TLV2541, TLV2542, TLV2545
2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS245E −MARCH 2000 − REVISED APRIL 2010

TYPICAL CHARACTERISTICS

SIGNAL-TO-NOISE + DISTORTION SIGNAL-TO-NOISE + DISTORTION

vs vs
INPUT FREQUENCY INPUT FREQUENCY
75 75
VDD = REF = 2.7 V VDD = REF = 5.5 V

SINAD − Signal-To-Noise + Distortion − dB

SINAD − Signal-To-Noise + Distortion − dB

150 KSPS 200 KSPS

73 73

71 71

69 69

67 67

65 65
0 10 20 30 40 50 60 70 80 0 20 40 60 80 100
f − Input Frequency − KHz f − Input Frequency − KHz

Figure 23 Figure 24

EFFECTIVE NUMBER OF BITS EFFECTIVE NUMBER OF BITS

vs vs
INPUT FREQUENCY INPUT FREQUENCY
12 12
VDD = REF = 2.7 V VDD = REF = 5.5 V
150 KSPS 11.9
ENOB − Effective Number Of Bits − Bits

200 KSPS
ENOB − Effective Number Of Bits − Bits

11.8 11.8

11.7
11.6 11.6

11.5
11.4 11.4

11.3
11.2 11.2

11.1
11 11
0 10 20 30 40 50 60 70 80 0 20 40 60 80 100
f − Input Frequency − KHz f − Input Frequency − KHz
Figure 25 Figure 26

•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 19
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
TLV2541, TLV2542, TLV2545
2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS245E −MARCH 2000 − REVISED APRIL 2010

TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
−75
VDD = REF = 2.7 V
−76 150 KSPS

THD − Total Harmonic Distortion − dB

−77

−78

−79

−80

−81

−82

−83

−84

−85
0 10 20 30 40 50 60 70 80
f − Input Frequency − KHz
Figure 27

TOTAL HARMONIC DISTORTION

vs
INPUT FREQUENCY
−70
VDD = REF = 5.5 V
−72 200 KSPS
THD − Total Harmonic Distortion − dB

−74

−76

−78

−80

−82

−84

−86

−88

−90
0 20 40 60 80 100
f − Input Frequency − KHz
Figure 28

20 •
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
 TLV2541, TLV2542, TLV2545
2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS245E −MARCH 2000 − REVISED APRIL 2010

APPLICATION INFORMATION
VDD VDD

10 kΩ
TLV2541
FS VDD
MISO SDO
SS CS AIN
SCLK SCLK
GND VREF
SPI PORT

EXT
Reference

(a)

VDD VDD

10 kΩ
TLV2541
FS VDD
DR SDO
CLKX
CLKR SCLK AIN

FSX CS
FSR GND VREF
DSP

EXT
Reference

(b)

VDD

TLV2541

FSX FS VDD
FSR
DR SDO
AIN
CLKX SCLK
CLKR
GPIO CS
DSP GND VREF

EXT
Reference

(c)

Figure 29. Typical TLV2541 Interface to a TMS320 DSP

•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 21
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
TLV2541, TLV2542, TLV2545
2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS245E −MARCH 2000 − REVISED APRIL 2010

APPLICATION INFORMATION
VDD

EXT
TMS320 10 kΩ
10 kΩ Reference
FSX VDD
FSR CS VREF
DR SDO
CLKR SCLK
CLKX
DSP TLV2542/45
AIN 0/AIN (+)†

GND AIN 1/AIN (−)†

† For TLV2545 only

Figure 30. Typical TLV2542/45 Interface to a TMS320 DSP

22 •
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
 PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

TLV2541CDGK ACTIVE VSSOP DGK 8 80 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM 0 to 70 AGZ

& no Sb/Br)
TLV2541CDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM 0 to 70 AGZ
& no Sb/Br)
TLV2541ID ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 2541I
& no Sb/Br)
TLV2541IDG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 2541I
& no Sb/Br)
TLV2541IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 AHA
& no Sb/Br)
TLV2541IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 AHA
& no Sb/Br)
TLV2541IDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 2541I
& no Sb/Br)
TLV2542CDGK ACTIVE VSSOP DGK 8 80 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM 0 to 70 AHB
& no Sb/Br)
TLV2542CDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM 0 to 70 AHB
& no Sb/Br)
TLV2542ID ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 2542I
& no Sb/Br)
TLV2542IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 AHC
& no Sb/Br)
TLV2542IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 AHC
& no Sb/Br)
TLV2542IDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 2542I
& no Sb/Br)
TLV2545CDGK ACTIVE VSSOP DGK 8 80 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM 0 to 70 AHD
& no Sb/Br)
TLV2545ID ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 2545I
& no Sb/Br)
TLV2545IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 AHE
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 26-Feb-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV2541CDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLV2541IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLV2541IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLV2542CDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLV2542IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLV2542IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 26-Feb-2019

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV2541CDGKR VSSOP DGK 8 2500 350.0 350.0 43.0
TLV2541IDGKR VSSOP DGK 8 2500 350.0 350.0 43.0
TLV2541IDR SOIC D 8 2500 350.0 350.0 43.0
TLV2542CDGKR VSSOP DGK 8 2500 350.0 350.0 43.0
TLV2542IDGKR VSSOP DGK 8 2500 350.0 350.0 43.0
TLV2542IDR SOIC D 8 2500 350.0 350.0 43.0

Pack Materials-Page 2
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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