LTC3407

Dual Synchronous, 600mA,

1.5MHz Step-Down
DC/DC Regulator
FEATURES DESCRIPTION
n High Efficiency: Up to 96% The LTC®3407 is a dual, constant frequency, synchronous
n Very Low Quiescent Current: Only 40μA step down DC/DC converter. Intended for low power ap-
n 1.5MHz Constant Frequency Operation plications, it operates from 2.5V to 5.5V input voltage
n High Switch Current: 1A on Each Channel range and has a constant 1.5MHz switching frequency,
n No Schottky Diodes Required allowing the use of tiny, low cost capacitors and inductors
n Low RDS(ON) Internal Switches: 0.35Ω 2mm or less in height. Each output voltage is adjustable
n Current Mode Operation for Excellent Line from 0.6V to 5V. Internal synchronous 0.35Ω, 1A power
and Load Transient Response switches provide high efficiency without the need for
n Short-Circuit Protected external Schottky diodes.
n Low Dropout Operation: 100% Duty Cycle
n
A user selectable mode input is provided to allow the user
Ultralow Shutdown Current: IQ < 1μA
n
to trade-off ripple noise for low power efficiency. Burst
Output Voltages from 5V down to 0.6V
n
Mode® operation provides high efficiency at light loads,
Power-On Reset Output
n
while pulse-skipping mode provides low ripple noise at
Externally Synchronizable Oscillator
n
light loads.
Small Thermally Enhanced MSOP and 3mm × 3mm
DFN Packages To further maximize battery life, the P-channel MOSFETs
are turned on continuously in dropout (100% duty cycle),
APPLICATIONS and both channels draw a total quiescent current of only
40μA. In shutdown, the device draws <1μA.
n PDAs/Palmtop PCs
L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks
n Digital Cameras of Linear Technology Corporation. All other trademarks are the property of their respective
n owners.
Cellular Phones
n Portable Media Players
n PC Cards
n Wireless and DSL Modems

TYPICAL APPLICATION
VIN = 2.5V LTC3407 Efficiency Curve
TO 5.5V
100
C1 R5
10μF RUN2 VIN RUN1 100k
95 2.5V
MODE/SYNC POR RESET
90 1.8V
LTC3407
EFFICIENCY (%)

L2 L1 85
2.2μH 2.2μH
VOUT2 = 2.5V VOUT1 = 1.8V
SW2 SW1 80
AT 600mA AT 600mA
C5, 22pF C4, 22pF
75

VFB2 VFB1 70
R4 R2 VIN = 3.3V
C3 R3 GND R1 887k C2
887k 65 Burst Mode OPERATION
10μF 280k 442k 10μF
NO LOAD ON OTHER CHANNEL
60
1 10 100 1000
LOAD CURRENT (mA)
C1, C2, C3: TAIYO YUDEN JMK316BJ106ML L1, L2: MURATA LQH32CN2R2M33 3407 TA01

3407 TA02

Figure 1. 2.5V/1.8V at 600mA Step-Down Regulators

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LTC3407
ABSOLUTE MAXIMUM RATINGS
(Note 1)
VIN Voltages .................................................– 0.3V to 6V Junction Temperature (Note 5) ............................. 125°C
VFB1, VFB2 Voltages .......................... –0.3V to VIN + 0.3V Storage Temperature Range
RUN1, RUN2 Voltages .................................–0.3V to VIN LTC3407EMSE ...................................– 65°C to 150°C
MODE/SYNC Voltage........................ –0.3V to VIN + 0.3V LTC3407EDD ...................................... –65°C to 125°C
SW1, SW2 Voltage ........................... –0.3V to VIN + 0.3V Lead Temperature (Soldering, 10 sec)
POR Voltage ................................................. –0.3V to 6V LTC3407EMSE only........................................... 300°C
Ambient Operating Temperature
Range (Note 2) .................................... –40°C to 85°C

PIN CONFIGURATION
TOP VIEW

TOP VIEW
VFB1 1 10 VFB2
RUN1 9 RUN2 VFB1 1 10 VFB2
2
VIN RUN1 2 9 RUN2
3 11 8 POR VIN 3 11 8 POR
SW1 4 7 SW2 SW1 4 7 SW2
GND GND 5 6 MODE/
5 6 MODE/ SYNC
SYNC MSE PACKAGE
10-LEAD PLASTIC MSOP
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 45°C/W, θJC = 10°C/W
EXPOSED PAD IS PGND (PIN 11) MUST BE CONNECTED TO GND
TJMAX = 125°C, θJA = 45°C/W, θJC = 10°C/W
EXPOSED PAD IS PGND (PIN 11) MUST BE CONNECTED TO GND

ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3407EDD#PBF LTC3407EDD#TRPBF LAGK 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC3407EMSE#PBF LTC3407EMSE#TRPBF LTABA 10-Lead (3mm × 3mm) Plastic MSOP –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, unless otherwise specified. (Note 2)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Operating Voltage Range ● 2.5 5.5 V
IFB Feedback Pin Input Current ● 30 nA
VFB Feedback Voltage (Note 3) 0°C ≤ TA ≤ 85°C 0.588 0.6 0.612 V
–40°C ≤ TA ≤ 85°C ● 0.585 0.6 0.612 V
ΔVLINE REG Reference Voltage Line Regulation VIN = 2.5V to 5.5V (Note 3) 0.3 0.5 %/V
ΔVLOAD REG Output Voltage Load Regulation (Note 3) 0.5 %
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 LTC3407
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, unless otherwise specified. (Note 2)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IS Input DC Supply Current
Active Mode VFB1 = VFB2 = 0.5V 600 800 μA
Sleep Mode VFB1 = VFB2 = 0.63V, MODE/SYNC = 3.6V 40 60 μA
Shutdown RUN = 0V, VIN = 5.5V, MODE/SYNC = 0V 0.1 1 μA
fOSC Oscillator Frequency VFBX = 0.6V ● 1.2 1.5 1.8 MHz
fSYNC Synchronization Frequency 1.5 MHz
ILIM Peak Switch Current Limit VIN = 3V, VFB = 0.5V, Duty Cycle <35% 0.75 1 1.25 A
RDS(ON) Top Switch On-Resistance (Note 6) 0.35 0.45 Ω
Bottom Switch On-Resistance (Note 6) 0.30 0.45 Ω
ISW(LKG) Switch Leakage Current VIN = 5V, VRUN = 0V, VFBX = 0V 0.01 1 μA
POR Power-On Reset Threshold VFBX Ramping Up, MODE/SYNC = 0V 8.5 %
VFBX Ramping Down, MODE/SYNC = 0V –8.5 %
Power-On Reset On-Resistance 100 200 Ω
Power-On Reset Delay 262,144 Cycles
VRUN RUN Threshold ● 0.3 1 1.5 V
IRUN RUN Leakage Current ● 0.01 1 μA
VMODE Mode Threshold Low 0 0.5 V
Mode Threshold High VIN – 0.5 VIN V

Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 3: The LTC3407 is tested in a proprietary test mode that connects VFB
may cause permanent damage to the device. Exposure to any Absolute to the output of the error amplifier.
Maximum Rating condition for extended periods may affect device Note 4: Dynamic supply current is higher due to the internal gate charge
reliability and lifetime. being delivered at the switching frequency.
Note 2: The LTC3407E is guaranteed to meet specified performance Note 5: TJ is calculated from the ambient TA and power dissipation PD
from 0°C to 70°C. Specifications over the – 40°C and 85°C operating according to the following formula: TJ = TA + (PD • θJA).
temperature range are assured by design, characterization and correlation
Note 6: The DFN switch on-resistance is guaranteed by correlation to
with statistical process controls.
wafer level measurements.

TYPICAL PERFORMANCE CHARACTERISTICS

Burst Mode Operation Pulse-Skipping Mode Load Step

SW SW VOUT
5V/DIV 5V/DIV 200mV/DIV

VOUT VOUT IL
100mV/DIV 10mV/DIV 500mA/DIV

IL IL ILOAD
200mA/DIV 200mA/DIV 500mA/DIV

3407 G01 3407 G03

VIN = 3.6V 4μs/DIV VIN = 3.6V 1μs/DIV 3407 G02 VIN = 3.6V 20μs/DIV
VOUT = 1.8V VOUT = 1.8V VOUT = 1.8V
ILOAD = 50mA ILOAD = 50mA ILOAD = 50mA TO 600mA
CIRCUIT OF FIGURE 1 CIRCUIT OF FIGURE 1 CIRCUIT OF FIGURE 1

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LTC3407
TYPICAL PERFORMANCE CHARACTERISTICS
Oscillator Frequency vs Oscillator Frequency vs Supply
Efficiency vs Input Voltage Temperature Voltage
100 1.70 1.8
TA = 25°C TA = 25°C
95 1.65
1.7

OSCILLATOR FREQUENCY (MHz)

100mA
90 1.60
1mA 10mA

FREQUENCY (MHz)
1.6
EFFICIENCY (%)

85 1.55
600mA
80 1.50 1.5

75 1.45
1.4
70 1.40
1.3
65 VOUT = 1.8V 1.35
CIRCUIT OF FIGURE 1
60 1.30 1.2
2 3 4 5 6 –50 –25 0 25 50 75 100 125 2 3 4 5 6
INPUT VOLTAGE (V) TEMPERATURE (°C) SUPPLY VOLTAGE (V)
3407 G04 3407 G05 3407 G06

Reference Voltage vs
Temperature RDS(ON) vs Input Voltage RDS(ON) vs Temperature
0.615 500 550
VIN = 3.6V TA = 25°C VIN = 2.7V
500
0.610 450 VIN = 3.6V
450 VIN = 4.2V
REFERENCE VOLTAGE (V)

0.605 400 MAIN 400

RDS(ON) (mΩ)

SWITCH RDS(ON) (mΩ)

350
0.600 350
300

0.595 300 250

SYNCHRONOUS
200
SWITCH
0.590 250
150 MAIN SWITCH
SYNCHRONOUS SWITCH
0.585 200 100
–50 –25 0 25 50 75 100 125 1 2 3 4 5 6 7 –50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C) VIN (V) TEMPERATURE (°C)
3407 G07 3407 G08 3407 G09

Efficiency vs Load Current Efficiency vs Load Current Load Regulation

100 100 4
2.7V
95 95 3 Burst Mode OPERATION
3.3V
Burst Mode OPERATION
90 4.2V 90 2
VOUT ERROR (%)
EFFICIENCY (%)
EFFICIENCY (%)

85 85 1

80 80 0
PULSE-SKIPPING PULSE-SKIPPING
75 75 MODE –1 MODE

70 70 –2

65 65 VIN = 3.6V, VOUT = 1.8V –3 VIN = 3.6V, VOUT = 1.8V

VOUT = 2.5V Burst Mode OPERATION
CIRCUIT OF FIGURE 1 NO LOAD ON OTHER CHANNEL NO LOAD ON OTHER CHANNEL
60 60 –4
1 10 100 1000 1 10 100 1000 1 10 100 1000
LOAD CURRENT (mA) LOAD CURRENT (mA) LOAD CURRENT (mA)
3407 G10 3407 G11 3407 G12

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 LTC3407
TYPICAL PERFORMANCE CHARACTERISTICS

Efficiency vs Load Current Efficiency vs Load Current Line Regulation

100 100 0.5
VOUT = 1.8V
95 0.4 IOUT = 200mA
95
3.3V 2.7V 3.3V 2.7V TA = 25°C
0.3
90 90
0.2

VOUT ERROR (%)

EFFICIENCY (%)

EFFICIENCY (%)
85 4.2V 85 4.2V
0.1
80 80 0

75 75 –0.1
–0.2
70 70
–0.3
65 65
VOUT = 1.2V Burst Mode OPERATION VOUT = 1.5V Burst Mode OPERATION –0.4
CIRCUIT OF FIGURE 1 CIRCUIT OF FIGURE 1
60 60 –0.5
1 10 100 1000 1 10 100 1000 2 3 4 5 6
LOAD CURRENT (mA) LOAD CURRENT (mA) VIN (V)
3407 G13 3407 G14 3407 G15

PIN FUNCTIONS
VFB1 (Pin 1): Output Feedback. Receives the feedback volt- synchronized to an external oscillator applied to this pin
age from the external resistive divider across the output. and pulse-skipping mode is automatically selected.
Nominal voltage for this pin is 0.6V.
SW2 (Pin 7): Regulator 2 Switch Node Connection to the
RUN1 (Pin 2): Regulator 1 Enable. Forcing this pin to VIN Inductor. This pin swings from VIN to GND.
enables regulator 1, while forcing it to GND causes regulator POR (Pin 8): Power-On Reset . This common-drain logic
1 to shut down. This pin must be driven; do not float. output is pulled to GND when the output voltage is not
VIN (Pin 3): Main Power Supply. Must be closely decoupled within ±8.5% of regulation and goes high after 175ms
to GND. when both channels are within regulation.
SW1 (Pin 4): Regulator 1 Switch Node Connection to the RUN2 (Pin 9): Regulator 2 Enable. Forcing this pin to VIN
Inductor. This pin swings from VIN to GND. enables regulator 2, while forcing it to GND causes regulator
GND (Pin 5): Ground. This pin is not connected internally. 2 to shut down. This pin must be driven; do not float.
Connect to PCB ground for shielding. VFB2 (Pin 10): Output Feedback. Receives the feedback
voltage from the external resistive divider across the output.
MODE/SYNC (Pin 6): Combination Mode Selection and
Nominal voltage for this pin is 0.6V.
Oscillator Synchronization. This pin controls the opera-
tion of the device. When tied to VIN or GND, Burst Mode Exposed Pad (GND) (Pin 11): Power Ground. Connect to
operation or pulse-skipping mode is selected, respectively. the (–) terminal of COUT, and (–) terminal of CIN. Must be
Do not float this pin. The oscillation frequency can be soldered to electrical ground on PCB.

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LTC3407
BLOCK DIAGRAM
REGULATOR 1
MODE/SYNC 6 BURST
CLAMP VIN

SLOPE
COMP

EN
0.6V + –
ITH SLEEP – + 5Ω
EA ICOMP
VFB1 1 – 0.35V +
BURST

S Q
RS
LATCH
R Q
0.55V – SWITCHING
UV LOGIC
UVDET
AND
+ BLANKING ANTI
CIRCUIT SHOOT-
THRU
4 SW1
+
OV
OVDET
0.65V – +
IRCMP
SHUTDOWN –
11 GND

VIN
3 VIN
PGOOD1
8 POR
RUN1 2
POR
0.6V REF OSC COUNTER
RUN2 9
OSC 5 GND
PGOOD2

REGULATOR 2 (IDENTICAL TO REGULATOR 1)

VFB2 10 7 SW2

3407 BD

OPERATION
The LTC3407 uses a constant frequency, current mode Main Control Loop
architecture. The operating frequency is set at 1.5MHz During normal operation, the top power switch (P-channel
and can be synchronized to an external oscillator. Both MOSFET) is turned on at the beginning of a clock cycle
channels share the same clock and run in-phase. To suit when the VFB voltage is below the the reference voltage.
a variety of applications, the selectable Mode pin allows The current into the inductor and the load increases until
the user to trade-off noise for efficiency. the current limit is reached. The switch turns off and
The output voltage is set by an external divider returned energy stored in the inductor flows through the bottom
to the VFB pins. An error amplifier compares the divided switch (N-channel MOSFET) into the load until the next
output voltage with a reference voltage of 0.6V and adjusts clock cycle.
the peak inductor current accordingly. Overvoltage and The peak inductor current is controlled by the internally
undervoltage comparators will pull the POR output low if compensated ITH voltage, which is the output of the er-
the output voltage is not within ±8.5%. The POR output ror amplifier. This amplifier compares the VFB pin to the
will go high after 262,144 clock cycles (about 175ms) of 0.6V reference. When the load current increases, the
achieving regulation. VFB voltage decreases slightly below the reference. This
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 LTC3407
OPERATION
decrease causes the error amplifier to increase the ITH For lower ripple noise at low currents, the pulse-skipping
voltage until the average inductor current matches the mode can be used. In this mode, the LTC3407 continues to
new load current. switch at a constant frequency down to very low currents,
where it will begin skipping pulses.
The main control loop is shut down by pulling the RUN
pin to ground. Dropout Operation
Low Current Operation When the input supply voltage decreases toward the
output voltage, the duty cycle increases to 100% which
Two modes are available to control the operation of the
is the dropout condition. In dropout, the PMOS switch is
LTC3407 at low currents. Both modes automatically switch
turned on continuously with the output voltage being equal
from continuous operation to to the selected mode when
to the input voltage minus the voltage drops across the
the load current is low.
internal P-channel MOSFET and the inductor.
To optimize efficiency, the Burst Mode operation can be
An important design consideration is that the RDS(ON)
selected. When the load is relatively light, the LTC3407
of the P-channel switch increases with decreasing input
automatically switches into Burst Mode operation in which
supply voltage (See Typical Performance Characteristics).
the PMOS switch operates intermittently based on load
Therefore, the user should calculate the power dissipation
demand with a fixed peak inductor current. By running
when the LTC3407 is used at 100% duty cycle with low
cycles periodically, the switching losses which are domi-
input voltage (See Thermal Considerations in the Applica-
nated by the gate charge losses of the power MOSFETs
tions Information Section).
are minimized. The main control loop is interrupted when
the output voltage reaches the desired regulated value. Low Supply Operation
A hysteretic voltage comparator trips when ITH is below
0.35V, shutting off the switch and reducing the power. The The LTC3407 incorporates an Under-Voltage Lockout circuit
output capacitor and the inductor supply the power to the which shuts down the part when the input voltage drops
load until ITH exceeds 0.65V, turning on the switch and the below about 1.65V to prevent unstable operation.
main control loop which starts another cycle.

APPLICATIONS INFORMATION
A general LTC3407 application circuit is shown in Figure 2. greater core losses, and lower output current capability. A
External component selection is driven by the load require- reasonable starting point for setting ripple current is ΔIL =
ment, and begins with the selection of the inductor L. Once 0.3 • ILIM, where ILIM is the peak switch current limit. The
the inductor is chosen, CIN and COUT can be selected. largest ripple current ΔIL occurs at the maximum input
voltage. To guarantee that the ripple current stays below a
Inductor Selection
specified maximum, the inductor value should be chosen
Although the inductor does not influence the operat-
according to the following equation:
ing frequency, the inductor value has a direct effect on
ripple current. The inductor ripple current ΔIL decreases V ⎛ V ⎞
L ≥ OUT • ⎜⎜1– OUT ⎟⎟
with higher inductance and increases with higher VIN or fO • ΔIL ⎝ VIN(MAX) ⎠
VOUT:
V ⎛ V ⎞ The inductor value will also have an effect on Burst Mode
ΔIL = OUT • ⎜1− OUT ⎟ operation. The transition from low current operation
fO • L ⎝ VIN ⎠ begins when the peak inductor current falls below a level
Accepting larger values of ΔIL allows the use of low set by the burst clamp. Lower inductor values result in
inductances, but results in higher output voltage ripple, higher ripple current which causes this to occur at lower
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LTC3407
APPLICATIONS INFORMATION
load currents. This causes a dip in efficiency in the upper Table 1. Representative Surface Mount Inductors
range of low current operation. In Burst Mode operation, PART VALUE DCR MAX DC SIZE
lower inductance values will cause the burst frequency NUMBER (μH) (Ω MAX) CURRENT (A) W × L × H (mm3)
to increase. Sumida 1.5 0.043 1.55 3.8 × 3.8 × 1.8
CDRH3D16 2.2 0.075 1.20
Inductor Core Selection 3.3 0.110 1.10
Different core materials and shapes will change the size/ 4.7 0.162 0.90

current and price/current relationship of an inductor. Toroid Sumida 2.2 0.116 0.950 3.5 × 4.3 × 0.8
CMD4D06 3.3 0.174 0.770
or shielded pot cores in ferrite or permalloy materials are 4.7 0.216 0.750
small and don’t radiate much energy, but generally cost Panasonic 3.3 0.17 1.00 4.5 × 5.4 × 1.2
more than powdered iron core inductors with similar ELT5KT 4.7 0.20 0.95
electrical characteristics. The choice of which style in- Murata 1.0 0.060 1.00 2.5 × 3.2 × 2.0
LQH32CN 2.2 0.097 0.79
ductor to use often depends more on the price vs size 4.7 0.150 0.65
requirements and any radiated field/EMI requirements
than on what the LTC3407 requires to operate. Table 1 Output Capacitor (COUT) Selection
shows some typical surface mount inductors that work The selection of COUT is driven by the required ESR to
well in LTC3407 applications. minimize voltage ripple and load step transients. Typically,
Input Capacitor (CIN) Selection once the ESR requirement is satisfied, the capacitance
In continuous mode, the input current of the converter is a is adequate for filtering. The output ripple (ΔVOUT) is
square wave with a duty cycle of approximately VOUT/VIN. determined by:
To prevent large voltage transients, a low equivalent series  
1
resistance (ESR) input capacitor sized for the maximum VOUT
IL ESR+ 
RMS current must be used. The maximum RMS capacitor  8fO COUT 
current is given by:
where f = operating frequency, COUT = output capacitance
VOUT (VIN – VOUT ) and ΔIL = ripple current in the inductor. The output ripple
IRMS ≈IMAX
VIN is highest at maximum input voltage since ΔIL increases
where the maximum average output current IMAX equals with input voltage. With ΔIL = 0.3 • ILIM the output ripple
the peak current minus half the peak-to-peak ripple cur- will be less than 100mV at maximum VIN and fO = 1.5MHz
rent, IMAX = ILIM – ΔIL/2. with:
ESRCOUT < 150mΩ
This formula has a maximum at VIN = 2VOUT, where IRMS
Once the ESR requirements for COUT have been met, the
= IOUT/2. This simple worst-case is commonly used to
RMS current rating generally far exceeds the IRIPPLE(P-P)
design because even significant deviations do not offer
requirement, except for an all ceramic solution.
much relief. Note that capacitor manufacturer’s ripple cur-
rent ratings are often based on only 2000 hours lifetime. In surface mount applications, multiple capacitors may
This makes it advisable to further derate the capacitor, have to be paralleled to meet the capacitance, ESR or RMS
or choose a capacitor rated at a higher temperature than current handling requirement of the application. Aluminum
required. Several capacitors may also be paralleled to meet electrolytic, special polymer, ceramic and dry tantulum
the size or height requirements of the design. An additional capacitors are all available in surface mount packages. The
0.1μF to 1μF ceramic capacitor is also recommended on OS-CON semiconductor dielectric capacitor available from
VIN for high frequency decoupling, when not using an all Sanyo has the lowest ESR(size) product of any aluminum
ceramic capacitor solution. electrolytic at a somewhat higher price. Special polymer

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 LTC3407
APPLICATIONS INFORMATION
capacitors, such as Sanyo POSCAP, offer very low ESR, caps are prone to temperature effects which requires the
but have a lower capacitance density than other types. designer to check loop stability over the operating tem-
Tantalum capacitors have the highest capacitance density, perature range. To minimize their large temperature and
but it has a larger ESR and it is critical that the capacitors voltage coefficients, only X5R or X7R ceramic capacitors
are surge tested for use in switching power supplies. should be used. A good selection of ceramic capacitors
An excellent choice is the AVX TPS series of surface is available from Taiyo Yuden, TDK, and Murata.
mount tantalums, available in case heights ranging from Great care must be taken when using only ceramic input
2mm to 4mm. Aluminum electrolytic capacitors have a and output capacitors. When a ceramic capacitor is used
significantly larger ESR, and are often used in extremely at the input and the power is being supplied through long
cost-sensitive applications provided that consideration wires, such as from a wall adapter, a load step at the output
is given to ripple current ratings and long term reliability. can induce ringing at the VIN pin. At best, this ringing can
Ceramic capacitors have the lowest ESR and cost, but also couple to the output and be mistaken as loop instability.
have the lowest capacitance density, a high voltage and At worst, the ringing at the input can be large enough to
temperature coefficient, and exhibit audible piezoelectric damage the part.
effects. In addition, the high Q of ceramic capacitors along
with trace inductance can lead to significant ringing. Other Since the ESR of a ceramic capacitor is so low, the input
capacitor types include the Panasonic special polymer and output capacitor must instead fulfill a charge storage
(SP) capacitors. requirement. During a load step, the output capacitor must
instantaneously supply the current to support the load
In most cases, 0.1μF to 1μF of ceramic capacitors should until the feedback loop raises the switch current enough
also be placed close to the LTC3407 in parallel with the to support the load. The time required for the feedback
main capacitors for high frequency decoupling. loop to respond is dependent on the compensation and
VIN = 2.5V
TO 5.5V the output capacitor size. Typically, 3-4 cycles are required
CIN
RUN2 VIN RUN1
R5 to respond to a load step, but only in the first cycle does
BURST*
PULSESKIP*
MODE/SYNC POR POWER-ON
RESET
the output drop linearly. The output droop, VDROOP, is
LTC3407 usually about 3 times the linear drop of the first cycle.
L2 L1
VOUT2 SW2 SW1 VOUT1 Thus, a good place to start is with the output capacitor
C5 C4
size of approximately:
VFB2 VFB1 ΔIOUT
R4
GND
R2
COUT ≈ 3
COUT2 R3 R1 COUT1
fO • VDROOP
3407 F02

*MODE/SYNC = 0V: PULSE-SKIPPING

MODE/SYNC = VIN: Burst Mode OPERATION
More capacitance may be required depending on the duty
Figure 2. LTC3407 General Schematic
cycle and load step requirements.
In most applications, the input capacitor is merely required
Ceramic Input and Output Capacitors to supply high frequency bypassing, since the impedance
Higher value, lower cost ceramic capacitors are now be- to the supply is very low. A 10μF ceramic capacitor is
coming available in smaller case sizes. These are tempting usually enough for these conditions.
for switching regulator use because of their very low ESR.
Setting the Output Voltage
Unfortunately, the ESR is so low that it can cause loop
stability problems. Solid tantalum capacitor ESR gener- The LTC3407 develops a 0.6V reference voltage between
ates a loop “zero” at 5kHz to 50kHz that is instrumental in the feedback pin, VFB, and the ground as shown in Figure 2.
giving acceptable loop phase margin. Ceramic capacitors The output voltage is set by a resistive divider according
remain capacitive to beyond 300kHz and usually resonate to the following formula:
with their ESL before ESR becomes effective. Also, ceramic
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LTC3407
APPLICATIONS INFORMATION
⎛ R2 ⎞ Checking Transient Response
VOUT = 0.6V ⎜1+ ⎟
⎝ R1 ⎠ The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
Keeping the current small (<5μA) in these resistors maxi- several cycles to respond to a step in load current. When
mizes efficiency, but making them too small may allow a load step occurs, VOUT immediately shifts by an amount
stray capacitance to cause noise problems and reduce the equal to ΔILOAD • ESR, where ESR is the effective series
phase margin of the error amp loop. resistance of COUT. ΔILOAD also begins to charge or dis-
To improve the frequency response, a feed-forward capaci- charge COUT generating a feedback error signal used by the
tor CF may also be used. Great care should be taken to regulator to return VOUT to its steady-state value. During
route the VFB line away from noise sources, such as the this recovery time, VOUT can be monitored for overshoot
inductor or the SW line. or ringing that would indicate a stability problem.
The initial output voltage step may not be within the
Power-On Reset bandwidth of the feedback loop, so the standard second-
The POR pin is an open-drain output which pulls low when order overshoot/DC ratio cannot be used to determine
either regulator is out of regulation. When both output volt- phase margin. In addition, a feed-forward capacitor, CF,
ages are within ±8.5% of regulation, a timer is started which can be added to improve the high frequency response, as
releases POR after 218 clock cycles (about 175ms). This shown in Figure 2. Capacitor CF provides phase lead by
delay can be significantly longer in Burst Mode operation creating a high frequency zero with R2 which improves
with low load currents, since the clock cycles only occur the phase margin.
during a burst and there could be milliseconds of time
between bursts. This can be bypassed by tying the POR The output voltage settling behavior is related to the stability
output to the MODE/SYNC input, to force pulse-skipping of the closed-loop system and will demonstrate the actual
mode during a reset. In addition, if the output voltage overall supply performance. For a detailed explanation of
faults during Burst Mode sleep, POR could have a slight optimizing the compensation components, including a re-
delay for an undervoltage output condition and may not view of control loop theory, refer to Application Note 76.
respond to an overvoltage output. This can be avoided by In some applications, a more severe transient can be caused
using pulse-skipping mode instead. When either channel by switching in loads with large (>1μF) input capacitors.
is shut down, the POR output is pulled low, since one or The discharged input capacitors are effectively put in paral-
both of the channels are not in regulation. lel with COUT, causing a rapid drop in VOUT. No regulator
can deliver enough current to prevent this problem, if the
Mode Selection & Frequency Synchronization
switch connecting the load has low resistance and is driven
The MODE/SYNC pin is a multipurpose pin which provides quickly. The solution is to limit the turn-on speed of the
mode selection and frequency synchronization. Connect- load switch driver. A Hot Swap™ controller is designed
ing this pin to VIN enables Burst Mode operation, which specifically for this purpose and usually incorporates cur-
provides the best low current efficiency at the cost of a rent limiting, short-circuit protection, and soft-starting.
higher output voltage ripple. When this pin is connected
to ground, pulse-skipping operation is selected which Efficiency Considerations
provides the lowest output ripple, at the cost of low cur-
rent efficiency. The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
The LTC3407 can also be synchronized to another LTC3407 It is often useful to analyze individual losses to determine
by the MODE/SYNC pin. During synchronization, the mode what is limiting the efficiency and which change would
is set to pulse-skipping and the top switch turn-on is syn- Hot Swap is a trademark of Linear Technology Corporation.
chronized to the rising edge of the external clock.

3407fa

10
 LTC3407
APPLICATIONS INFORMATION
produce the most improvement. Percent efficiency can to include these “system” level losses in the design of a
be expressed as: system. The internal battery and fuse resistance losses
%Efficiency = 100% - (L1 + L2 + L3 + ...) can be minimized by making sure that CIN has adequate
charge storage and very low ESR at the switching frequency.
where L1, L2, etc. are the individual losses as a percent- Other losses including diode conduction losses during
age of input power. dead-time and inductor core losses generally account for
Although all dissipative elements in the circuit produce less than 2% total additional loss.
losses, 4 main sources usually account for most of the
Thermal Considerations
losses in LTC3407 circuits: 1)VIN quiescent current, 2)
switching losses, 3) I2R losses, 4) other losses. In a majority of applications, the LTC3407 does not dis-
1) The VIN current is the DC supply current given in the sipate much heat due to its high efficiency. However, in
Electrical Characteristics which excludes MOSFET driver applications where the LTC3407 is running at high ambient
and control currents. VIN current results in a small (<0.1%) temperature with low supply voltage and high duty cycles,
loss that increases with VIN, even at no load. such as in dropout, the heat dissipated may exceed the
maximum junction temperature of the part. If the junction
2) The switching current is the sum of the MOSFET driver temperature reaches approximately 150°C, both power
and control currents. The MOSFET driver current results switches will be turned off and the SW node will become
from switching the gate capacitance of the power MOSFETs. high impedance.
Each time a MOSFET gate is switched from low to high
to low again, a packet of charge dQ moves from VIN to To prevent the LTC3407 from exceeding the maximum
ground. The resulting dQ/dt is a current out of VIN that is junction temperature, the user will need to do some thermal
typically much larger than the DC bias current. In continu- analysis. The goal of the thermal analysis is to determine
ous mode, IGATECHG = fO(QT + QB), where QT and QB are whether the power dissipated exceeds the maximum
the gate charges of the internal top and bottom MOSFET junction temperature of the part. The temperature rise is
switches. The gate charge losses are proportional to VIN given by:
and thus their effects will be more pronounced at higher TRISE = PD • θJA
supply voltages. where PD is the power dissipated by the regulator and θJA
3) I2R losses are calculated from the DC resistances of the is the thermal resistance from the junction of the die to
internal switches, RSW, and external inductor, RL. In con- the ambient temperature.
tinuous mode, the average output current flowing through
The junction temperature, TJ, is given by:
inductor L, but is “chopped” between the internal top and
bottom switches. Thus, the series resistance looking into TJ = TRISE + TAMBIENT
the SW pin is a function of both top and bottom MOSFET As an example, consider the case when the LTC3407 is
RDS(ON) and the duty cycle (DC) as follows: in dropout on both channels at an input voltage of 2.7V
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC) with a load current of 600mA and an ambient temperature
of 70°C. From the Typical Performance Characteristics
The RDS(ON) for both the top and bottom MOSFETs can
graph of Switch Resistance, the RDS(ON) resistance of
be obtained from the Typical Performance Characteristics the main switch is 0.425Ω. Therefore, power dissipated
curves. Thus, to obtain I2R losses: by each channel is:
I2R losses = (IOUT)2 (RSW + RL)
PD = IOUT2 • RDS(ON) = 153mW
4) Other ‘hidden’ losses such as copper trace and internal The MS package junction-to-ambient thermal resistance,
battery resistances can account for additional efficiency θJA, is 45°C/W. Therefore, the junction temperature of
degradations in portable systems. It is very important
3407fa

11
LTC3407
APPLICATIONS INFORMATION
the regulator operating in a 70°C ambient temperature is Board Layout Considerations
approximately:
When laying out the printed circuit board, the following
TJ = 2 • 0.153 • 45 + 70 = 84°C checklist should be used to ensure proper operation of
which is below the absolute maximum junction tempera- the LTC3407. These items are also illustrated graphically
ture of 125°C. in the layout diagram of Figure 3. Check the following in
your layout:
Design Example 1. Does the capacitor CIN connect to the power VIN (Pin
As a design example, consider using the LTC3407 in an 3) and GND (exposed pad) as close as possible? This
portable application with a Li-Ion battery. The battery pro- capacitor provides the AC current to the internal power
vides a VIN = 2.8V to 4.2V. The load requires a maximum MOSFETs and their drivers.
of 600mA in active mode and 2mA in standby mode. The 2. Are the COUT and L1 closely connected? The (–) plate of
output voltage is VOUT = 2.5V. Since the load still needs COUT returns current to GND and the (–) plate of CIN.
power in standby, Burst Mode operation is selected for
good low load efficiency. 3. The resistor divider, R1 and R2, must be connected
between the (+) plate of COUT and a ground sense line
First, calculate the inductor value for about 30% ripple terminated near GND (Exposed Pad). The feedback signals
current at maximum VIN: VFB should be routed away from noisy components and
2.5V ⎛ 2.5V ⎞ traces, such as the SW line (Pins 4 and 7), and its trace
L≥ • ⎜1– ⎟ = 2.25μH
1.5MHz • 300mA ⎝ 4.2V ⎠ should be minimized.
4. Keep sensitive components away from the SW pins. The
Choosing the closest inductor from a vendor of 2.2μH input capacitor CIN and the resistors R1 to R4 should be
inductor, results in a maximum ripple current of:
routed away from the SW traces and the inductors.
2.5V ⎛ 2.5V ⎞
ΔIL = • ⎜1− ⎟ = 307mA 5. A ground plane is preferred, but if not available, keep
1.5MHz • 2.2μH ⎝ 4.2V ⎠ the signal and power grounds segregated with small signal
components returning to the GND pin at one point and
For cost reasons, a ceramic capacitor will be used. COUT
should not share the high current path of CIN or COUT.
selection is then based on load step droop instead of ESR
requirements. For a 5% output droop: 6. Flood all unused areas on all layers with copper. Flood-
600mA ing with copper will reduce the temperature rise of power
COUT ≈ 3 = 9.6μF components. These copper areas should be connected to
1.5MHz • (5% • 2.5V) VIN or GND.
The closest standard value is 10μF. Since the output imped- VIN
ance of a Li-Ion battery is very low, CIN is typically 10μF. CIN
RUN2 VIN RUN1
The output voltage can now be programmed by choosing MODE/SYNC POR
the values of R1 and R2. To maintain high efficiency, the LTC3407
current in these resistors should be kept small. Choosing VOUT2
L2
SW2 SW1
L1
VOUT1
2μA with the 0.6V feedback voltage makes R1~300k. A close C5 C4

standard 1% resistor is 280k, and R2 is then 887k.

VFB2 VFB1

The POR pin is a common drain output and requires a pull-

R4 R2
GND
COUT2 R3 R1 COUT1
up resistor. A 100k resistor is used for adequate speed.
Figure 1 shows the complete schematic for this design 3407 F03

BOLD LINES INDICATE HIGH CURRENT PATHS

example.
Figure 3. LTC3407 Layout Diagram (See Board Layout Checklist)

3407fa

12
 LTC3407
TYPICAL APPLICATIONS
Low Ripple Buck Regulators Using Ceramic Capacitors

VIN = 2.5V
TO 5.5V
C1 R5
10μF RUN2 VIN RUN1 100k
POWER-ON
POR
RESET

L2 LTC3407 L1
4.7μH 4.7μH
VOUT2 = 1.8V VOUT1 = 1.2V
SW2 SW1
AT 600mA AT 600mA
C5, 22pF C4, 22pF

VFB2 VFB1
R4 R2
C3 R3 MODE/SYNC GND R1 604k C2
887k
10μF 442k 604k 10μF

C1, C2, C3: TAIYO YUDEN JMK316BJ106ML L1, L2: MURATA LQH32CN4R7M11 3407 TA03

Efficiency
100

95
VOUT = 1.8V
90
EFFICIENCY (%)

85 VOUT = 1.2V

80

75

70

65 VIN = 3.3V Burst Mode OPERATION

NO LOAD ON OTHER CHANNEL
60
1 10 100 1000
LOAD CURRENT (mA)
3407 TA03b

3407fa

13
LTC3407
TYPICAL APPLICATIONS
2mm Height Core Supply

VIN = 3.6V
TO 5.5V
C1 R5
10μF RUN2 VIN RUN1 100k
POWER-ON
MODE/SYNC POR
RESET

L2 LTC3407 L1
4.7μH 2.2μH
VOUT2 = 3.3V VOUT1 = 1.8V
SW2 SW1
AT 600mA AT 600mA
C5, 22pF C4, 22pF

VFB2 VFB1
R4 R2
C3 R3 GND R1 604k C2
887k
10μF 196k 301k 10μF

C1, C2, C3: TAIYO YUDEN JMK316BJ106ML 3407 TA07

L1: MURATA LQH32CN2R2M33

L2: MURATA LQH32CN4R7M11

Efficiency vs Load Current

100

95 3.3V

90
EFFICIENCY (%)

85 1.8V

80

75

70

65 VIN = 5V Burst Mode OPERATION

NO LOAD ON OTHER CHANNEL
60
1 10 100 1000
LOAD CURRENT (mA)
3407 TA08

3407fa

14
 LTC3407
PACKAGE DESCRIPTION
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699 Rev B)

R = 0.125 0.40 ± 0.10

TYP
6 10
0.70 ±0.05

3.55 ±0.05 1.65 ±0.05 3.00 ±0.10 1.65 ± 0.10

2.15 ±0.05 (2 SIDES) (4 SIDES) (2 SIDES)
PIN 1
PACKAGE TOP MARK
OUTLINE (SEE NOTE 6)
(DD) DFN REV B 0309

5 1
0.25 ± 0.05 0.200 REF 0.75 ±0.05 0.25 ± 0.05
0.50 0.50 BSC
BSC 2.38 ±0.10
2.38 ±0.05 (2 SIDES)
0.00 – 0.05
(2 SIDES) BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE

MSE Package
10-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1664 Rev C)

BOTTOM VIEW OF
3.00 ± 0.102
2.794 ± 0.102 EXPOSED PAD OPTION
0.889 ± 0.127 (.118 ± .004)
(.110 ± .004) 0.497 ± 0.076 2.06 ± 0.102
(.035 ± .005) (NOTE 3) (.0196 ± .003) 1 (.081 ± .004)
10 9 8 7 6
REF
1.83 ± 0.102
(.072 ± .004)
5.23 DETAIL “A” 3.00 ± 0.102
2.083 ± 0.102 3.20 – 3.45 0.254 4.90 ± 0.152
(.206) (.118 ± .004)
(.082 ± .004) (.126 – .136) (.010) (.193 ± .006)
MIN 0° – 6° TYP (NOTE 4)
GAUGE PLANE
DETAIL “B”
0.53 ± 0.152
0.305 ± 0.038 0.50 (.021 ± .006) 1 2 3 4 5 10
(.0120 ± .0015) (.0197)
TYP BSC DETAIL “A” 1.10 0.86 0.29
RECOMMENDED SOLDER PAD LAYOUT 0.18 (.043) (.034) REF
(.007) MAX REF

NOTE: 0.05 REF

SEATING
1. DIMENSIONS IN MILLIMETER/(INCH) PLANE DETAIL “B”
2. DRAWING NOT TO SCALE 0.17 – 0.27 0.1016 ± 0.0508
CORNER TAIL IS PART OF
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. (.007 – .011) (.004 ± .002)
0.50 THE LEADFRAME FEATURE.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE TYP
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. (.0197) FOR REFERENCE ONLY
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE BSC NO MEASUREMENT PURPOSE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX MSOP (MSE) 0908 REV C

3407fa

15
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC3407
TYPICAL APPLICATION
2mm Height Lithium-Ion Single Inductor Buck-Boost Regulator and a Buck Regulator
VIN = 2.8V
TO 4.2V
C1 R5
10μF RUN2 VIN RUN1 100k
POWER-ON
MODE/SYNC POR
RESET

L2 LTC3407 L1
D1 10μH 2.2μH
VOUT2 = 3.3V VOUT1 = 1.8V
SW2 SW1
AT 200mA AT 600mA
C4, 22pF
M1

+ C6
VFB2 VFB1
47μF R4 R2
C3 GND C2
887k R3 R1 887k
10μF 196k 442k 10μF

C1, C2, C3: TAIYO YUDEN JMK316BJ106ML L1: MURATA LQH32CN2R2M33 3407 TA04

C6: SANYO 6TPB47M L2: TOKO A914BYW-100M (D52LC SERIES)

D1: PHILIPS PMEG2010 M1: SILICONIX Si2302

Efficiency vs Load Current Efficiency vs Load Current

90 100

95
80 2.8V
90 3.6V
4.2V
70 4.2V

EFFICIENCY (%)
EFFICIENCY (%)

2.8V 85
3.6V
60 80

75
50
70
40 VOUT = 3.3V VOUT = 1.8V
Burst Mode OPERATION 65 Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL NO LOAD ON OTHER CHANNEL
30 60
1 10 100 1000 1 10 100 1000
LOAD CURRENT (mA) LOAD CURRENT (mA)
3407 TA05 3407 TA06

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ThinSOT is a trademark of Linear Technology Corporation.
3407fa

LT 0809 REV A • PRINTED IN USA

16 Linear Technology Corporation

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