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9 stars written in SystemVerilog
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Proving leftpad correct two-dozen different ways

SystemVerilog 705 64 Updated Apr 21, 2025

A eurorack-friendly audio frontend compatible with many FPGA boards, based on the AK4619VN audio CODEC.

SystemVerilog 221 16 Updated Jun 26, 2025

Kria Vitis platforms and overlays

SystemVerilog 107 52 Updated May 17, 2025

Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components

SystemVerilog 76 13 Updated Apr 11, 2022

MIPI CSI-2 RX

SystemVerilog 37 11 Updated Oct 20, 2021

Multi-Processor System on Chip verified with UVM/OSVVM/FV

SystemVerilog 35 16 Updated May 26, 2025

MIL-STD-1553 <-> SPI bridge

SystemVerilog 30 6 Updated Sep 4, 2018
SystemVerilog 2 Updated Aug 14, 2019

just a minimal tcl setup for running Vivado synthesis on a self-contained design

SystemVerilog 1 Updated Jul 30, 2020