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opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our d…
Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.
An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。
A tiny Open POWER ISA softcore written in VHDL 2008
synthesiseable ieee 754 floating point library in verilog
Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks
An open source library for image processing on FPGA.
A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。
Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation
Docs, design, firmware, and software for the Haasoscope
Betrusted main SoC design
Imitate SDcard using FPGAs. 使用FPGA模拟伪装SD卡。
A single-wire bi-directional chip-to-chip interface for FPGAs
Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker
Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples => https://www.chili-chips.xyz/open-cologne | Also see https:/…
A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs
MIPI CSI-2 Camera Sensor Receiver V2 Verilog HDL implementation For any generic FPGA. Tested with IMX219 IMX477 on Lattice Crosslink NX with Hard MIPI PHY. Gbps UVC Video Stream Over USB 3.0 with C…
Small SERV-based SoC primarily for OpenMPW tapeout
This repository contains software for BeagleWire. It is a realization of my project for GSOC-2017
This repo is for Efinix Xyloni development board users. It has projects and software to get you started working with the board.
Open-source CSI-2 receiver for Xilinx UltraScale parts
Flexible Byte transport protocol for bus bridging CPUs to FPGAs over UART,SPI,SERDES physical interfaces