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50 stars written in Verilog
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opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Verilog 2,544 322 Updated Apr 27, 2026

Open source FPGA-based NIC and platform for in-network compute

Verilog 2,286 530 Updated Jul 5, 2024

A small, light weight, RISC CPU soft core

Verilog 1,531 178 Updated Dec 8, 2025

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our d…

Verilog 1,328 34 Updated Mar 12, 2026

32-bit Superscalar RISC-V CPU

Verilog 1,240 201 Updated Sep 18, 2021

Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.

Verilog 1,101 210 Updated Mar 27, 2026

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器,用于驱动BLDC/PMSM电机。

Verilog 885 257 Updated Sep 15, 2023

synthesiseable ieee 754 floating point library in verilog

Verilog 734 158 Updated Mar 13, 2023

A tiny Open POWER ISA softcore written in VHDL 2008

Verilog 717 117 Updated Apr 25, 2026

Bus bridges and other odds and ends

Verilog 662 126 Updated Mar 10, 2026

An open source library for image processing on FPGA.

Verilog 632 224 Updated Jun 16, 2015

Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks

Verilog 623 102 Updated Jan 3, 2020

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

Verilog 450 103 Updated Dec 2, 2019

An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。

Verilog 341 97 Updated Sep 15, 2023

Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation

Verilog 294 47 Updated Feb 11, 2024

Betrusted main SoC design

Verilog 160 24 Updated Jul 22, 2025

Docs, design, firmware, and software for the Haasoscope

Verilog 155 47 Updated May 24, 2024

Imitate SDcard using FPGAs. 使用FPGA模拟伪装SD卡。

Verilog 135 28 Updated Sep 14, 2023

A single-wire bi-directional chip-to-chip interface for FPGAs

Verilog 125 16 Updated Jul 7, 2016
Verilog 125 29 Updated Sep 2, 2023

Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker

Verilog 104 13 Updated Feb 17, 2023

Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples => https://www.chili-chips.xyz/open-cologne | Also see https:/…

Verilog 96 8 Updated Feb 26, 2026

MIPI CSI-2 Camera Sensor Receiver V2 Verilog HDL implementation For any generic FPGA. Tested with IMX219 IMX477 on Lattice Crosslink NX with Hard MIPI PHY. Gbps UVC Video Stream Over USB 3.0 with C…

Verilog 67 30 Updated Feb 13, 2025

A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs

Verilog 64 14 Updated Jan 8, 2019

Small SERV-based SoC primarily for OpenMPW tapeout

Verilog 51 13 Updated Dec 18, 2025

This repo is for Efinix Xyloni development board users. It has projects and software to get you started working with the board.

Verilog 46 8 Updated Jan 16, 2023

This repository contains software for BeagleWire. It is a realization of my project for GSOC-2017

Verilog 46 16 Updated Oct 10, 2018
Verilog 45 2 Updated May 8, 2020

Development board for GateMateA1 CCGM1A1 FPGA from Cologne Chip with PS2 VGA 64Mbit RAM RP2040

Verilog 42 1 Updated Mar 24, 2026

migen + misoc + redpitaya = digital servo

Verilog 40 6 Updated Jan 11, 2019
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