Stars
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
VUnit is a unit testing framework for VHDL/SystemVerilog
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
The PoC Library has been forked to github.com/VHDL/PoC. See new address below
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.
UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improv…
💻 A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL
Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
Software Defined Radio in FPGA uses LVDS IO pins as 1-bit ADC
implement PCIE devices using C or VHDL and test them against a QEMU virtualized architecture
Original hand-coded firmware for the HDMI2USB - HDMI/DVI Capture - project
A repository of IPs for hardware computer vision (FPGA)
ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 architecture, now changed to RISC-V ISA.
Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
Trying to verify Verilog/VHDL designs with formal methods and tools
A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
Baseband Receiver IP for GPS like DSSS signals
A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models