PicoRV32 - A Size-Optimized RISC-V CPU

Verilog Ethernet components for FPGA implementation

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Open source FPGA-based NIC and platform for in-network compute

IC design and development should be faster，simpler and more reliable

Verilog AXI components for FPGA implementation

HDL libraries and projects

Verilog PCI express components

Verilog library for ASIC and FPGA designers

An Open-source FPGA IP Generator

MNT VA2000, an Open Source Amiga 2/3/4000 Graphics Card (Zorro II/III), written in Verilog

The RIFFA development repository

Various HDL (Verilog) IP Cores

A tiny Open POWER ISA softcore written in VHDL 2008

Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks

Bus bridges and other odds and ends

VRoom! RISC-V CPU

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

Defines a lossless compressed data format that is independent of CPU type, operating system, file system, and character set, and is suitable for compression using the XP10 algorithm.

High throughput JPEG decoder in Verilog for FPGA

A full-speed device-side USB peripheral core written in Verilog.

Deep Learning Accelerator (Convolution Neural Networks)

Compact FPGA game console

A compact USB HID host FPGA core supporting keyboards, mice and gamepads.

MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.

Chisel components for FPGA projects