SystemVerilog frontend for Yosys

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A vim color scheme based on the builder-dark theme from Gnome Builder

SystemVerilog compiler and language services

Structural Netlist API (and more) for EDA post synthesis flow development

Fil-C: completely compatible memory safety for C and C++

A minimal GPU design in Verilog to learn how GPUs work from the ground up

🌸 A command-line fuzzy finder

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

Get up and running with OpenAI gpt-oss, DeepSeek-R1, Gemma 3 and other models.

Ceilings - Rustlings and Ziglings for C!

Making cocotb testbenches that bit easier

Un regroupement de notebooks pour apprendre le deep learning à partir de 0

Repository gathering basic modules for CDC purpose

Minimal, fast, and extensible fuzzy finder.

Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.

GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.

A compact USB HID host FPGA core supporting keyboards, mice and gamepads.

Collection of Vim themes with barely any colors

A color scheme for Neovim

LLM inference in C/C++

The simplest, fastest repository for training/finetuning medium-sized GPTs.

Pool arena implementation

Templated type-safe hashmap implementation in C using open addressing and linear probing for collision resolution.

Convert any music library into a music production sample-library with ML

Learn about the Neumorphic engineering process of creating large-scale integration (VLSI) systems containing electronic analog circuits to mimic neuro-biological architectures.

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

RISC-V Verification Interface