Skip to content
View dpretet's full-sized avatar
:octocat:
:octocat:
202 followers · 287 following

Achievements

Achievement: Starstruckx2Achievement: Public SponsorAchievement: Arctic Code Vault ContributorAchievement: Pull Shark

Achievements

Achievement: Starstruckx2Achievement: Public SponsorAchievement: Arctic Code Vault ContributorAchievement: Pull Shark

Block or report dpretet

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Lists (8)

Sort Name ascending (A-Z)
Sort by
Name ascending (A-Z) Name descending (Z-A) Newest Oldest Last updated

Starred repositories

4 results for sponsorable starred repositories written in Verilog
Clear filter

ultraembedded / cores

Various HDL (Verilog) IP Cores

Verilog 842 226 Updated Jul 1, 2021

dpretet / async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Verilog 387 93 Updated Sep 16, 2025

ultraembedded / core_jpeg

High throughput JPEG decoder in Verilog for FPGA

Verilog 244 48 Updated Mar 5, 2022

ultraembedded / core_uriscv

Another tiny RISC-V implementation

Verilog 59 16 Updated Jul 19, 2021

Starred topics