Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。

Human Resource Machine - CPU Design #HRM

Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)

Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.

Digital Logic Design course project , Fall of 2024

This repository contains the implementation of an SPI (Serial Peripheral Interface) communication protocol with single port sync RAM.

A finite state machine controlled calculator written using Verilog in Xilinx Vivado targeting the Nexys 4 DDR FPGA Board

This repository contains a collection of small Verilog modules for various purposes.

Verilog Code Challenge – KVLSI Kohort 2

Complex Adder with Seven Segment Display

FSM: Sequence Detector using Verilog HDL

Desenvolvimento de uma aplicação sobre sobre Máquina de Estados Finita, desenvolvida nos dois modelos de comunicação: Síncrona e Assíncrona, para a disciplina de Arquitetura de Computadores II Unisinos-2019.

RTL to GDS II flow for a custom "Oven FSM" ASIC design utilising Qflow, an Open Source Physical Design toolchain.

A Verilog HDL-based vending machine project using FSM and simulated in Xilinx Vivado.

SerDes RTL design, verification using UVM and Physical design.

Design a Stopwatch with Verilog HDL

Interactive memory game implemented in Verilog and deployed on Nexys-A7 FPGA using FSM-based logic.

Verilog Programs

Using finite state machine (FSM) approach to design a traffic light controller on Altera DE1 development board.