Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。

Human Resource Machine - CPU Design #HRM

Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)

Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.

Digital Logic Design course project , Fall of 2024

This repository contains the implementation of an SPI (Serial Peripheral Interface) communication protocol with single port sync RAM.

This repository contains a collection of small Verilog modules for various purposes.

Verilog Code Challenge – KVLSI Kohort 2

The core system uses a Finite State Machine (FSM) to handle sequential serial protocols. By passing system parameters, the architecture recalculates internal counters to support variable bandwidths (9600, 115200, and 1 Mbps). It is mapped to run on standard FPGA boards (such as Basys 3 or Nexys A7) driven by a 100 MHz onboard crystal oscillator.

Design a Stopwatch with Verilog HDL

Complex Adder with Seven Segment Display

SerDes RTL design, verification using UVM and Physical design.

FSM: Sequence Detector using Verilog HDL

A Verilog HDL-based vending machine project using FSM and simulated in Xilinx Vivado.

Desenvolvimento de uma aplicação sobre sobre Máquina de Estados Finita, desenvolvida nos dois modelos de comunicação: Síncrona e Assíncrona, para a disciplina de Arquitetura de Computadores II Unisinos-2019.

Verilog RTL implementation of a multi-floor elevator controller with FSM-based control and simulation testbench.

RTL to GDS II flow for a custom "Oven FSM" ASIC design utilising Qflow, an Open Source Physical Design toolchain.

Interactive memory game implemented in Verilog and deployed on Nexys-A7 FPGA using FSM-based logic.

Verilog Programs