Comparative study of Mealy vs Moore FSM architectures in Verilog - Multi-item vending machine controller with timing analysis, and power metrics (79-81.5MHz on Artix-7)

This Include Every verilog code of most of Digital Electronics .

Digital Locker implemented in Verilog HDL using a Finite State Machine (FSM). Unlocks with sequence 1010, includes simulation, RTL schematic, and documentation.

Fully functional RISC-V compatible multicycle CPU built in Verilog. Includes ALU, datapath, FSM controller, memory, and testbenches.

Router 1x3 Design and Verification in Verilog

Sensor-aware 4-road traffic light controller using Finite State Machine in Verilog. Dynamically manages traffic flow with priority-based signal allocation, timer-controlled phase transitions, and real-time traffic monitoring for smart city applications.

This repository contains two Verilog modules—a 4-bit synchronous up-counter and an input-triggered finite state machine (FSM)—along with simulation testbenches. Designed to demonstrate clock-driven logic, memory retention, and real-time state transitions using edge detection and synchronous resets.

Human Resource Machine - CPU Design #HRM

Verilog Code Challenge – KVLSI Kohort 2

A reliable drone flight data recorder designed with FPGA logic to capture and store real-time trajectory (x,y,z) and attitude (Roll, Pitch, Yaw) data.

This repository consists of four projects or "labs" which were developed for the needs of the course "Digital Systems Lab". This course is part of the undergraduate studies of University of Thessally - ECE Department located in Volos, Greece.

ALU Built with proper Datapath and Control path (FSM) to give appropriate results

A Verilog HDL-based vending machine project using FSM and simulated in Xilinx Vivado.

RTL designs and simulations for FIFO buffers (Synchronous & Asynchronous) in Verilog, targeting robust data handling architectures.

Interactive memory game implemented in Verilog and deployed on Nexys-A7 FPGA using FSM-based logic.

TU/E related course repo (5EIC0)

Reaction Time Testing Game

Interface with LCD using I2C protocol in Verilog

This repository contains the implementation of an SPI (Serial Peripheral Interface) communication protocol with single port sync RAM.

Design a led 7 seg counter, demo how to interface with HC595 ic