Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)

Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。

Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.

Human Resource Machine - CPU Design #HRM

A finite state machine controlled calculator written using Verilog in Xilinx Vivado targeting the Nexys 4 DDR FPGA Board

Using finite state machine (FSM) approach to design a traffic light controller on Altera DE1 development board.

This repository contains the implementation of an SPI (Serial Peripheral Interface) communication protocol with single port sync RAM.

Desenvolvimento de uma aplicação sobre sobre Máquina de Estados Finita, desenvolvida nos dois modelos de comunicação: Síncrona e Assíncrona, para a disciplina de Arquitetura de Computadores II Unisinos-2019.

Complex Adder with Seven Segment Display

Digital Logic Design course project , Fall of 2024

Design a Stopwatch with Verilog HDL

This repository contains a collection of small Verilog modules for various purposes.

Digital Locker implemented in Verilog HDL using a Finite State Machine (FSM). Unlocks with sequence 1010, includes simulation, RTL schematic, and documentation.

Router 1x3 Design and Verification in Verilog

This repository consists of four projects or "labs" which were developed for the needs of the course "Digital Systems Lab". This course is part of the undergraduate studies of University of Thessally - ECE Department located in Volos, Greece.

FSM: Sequence Detector using Verilog HDL

Fully functional RISC-V compatible multicycle CPU built in Verilog. Includes ALU, datapath, FSM controller, memory, and testbenches.

This repository contains two Verilog modules—a 4-bit synchronous up-counter and an input-triggered finite state machine (FSM)—along with simulation testbenches. Designed to demonstrate clock-driven logic, memory retention, and real-time state transitions using edge detection and synchronous resets.

RTL designs and simulations for FIFO buffers (Synchronous & Asynchronous) in Verilog, targeting robust data handling architectures.