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hdl

Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.

Here are 25 public repositories matching this topic...

Pconst167 / sol-1

Sol-1: A CPU/Computer System made from 74 series logic.

unix cpu electronics assembly assembler operating-system verilog c-compiler hdl

Updated Nov 4, 2025
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FedericoSerafini / HLS-CNN

High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.

asic fpga stream hls pipeline hardware accelerator parallel cnn rtl synthesis hdl high-level-synthesis vitis

Updated Jul 25, 2024
C

myriadrf / FreeSRP_GW

The FPGA design for the FreeSRP's Artix 7 FPGA

fpga hdl

Updated Apr 12, 2017
C

Goshik92 / multicore-nios

Matrix multiplication on multiple Nios II cores

fpga parallel-computing matrix-multiplication verilog mailbox nios shared-memory hdl fpga-soc qsys parallel-programming nios2 de2-115 quartus spmd sopc platform-designer

Updated Feb 12, 2020
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voldemoriarty / Matmul

Matrix Multiplication in Hardware

fpga matrix-multiplication xilinx altera hdl hardware-acceleration spinalhdl nios-ii

Updated Jun 3, 2020
C

egorxe / openglory

Open source GPU in VHDL

gpu hdl

Updated Feb 25, 2025
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pepsipu / ban

Boolean Algebra Notation is a programming language that allows the execution of Boolean expressions.

c programming-language simulator latex math boolean-algebra hdl

Updated Jun 10, 2019
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A-framework-for-developing-Neural-Networks-in-hardware-accelerators

georgevangelou / A-framework-for-developing-Neural-Networks-in-hardware-accelerators

This framework was part of the Diploma thesis titled "Architectures and Implementations of the Neural Network LeNet-5 in FPGAs". The main goal of this thesis was to create a LeNet-5 implementation in an FPGA development board, but also form a reusable framework/workflow which can be modified to model and develop other Neural Networks as well.

hls thesis lenet hdl ristretto vivado-hls

Updated May 6, 2022
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agkaminski / AK6502

Verilog implementation and C simulator of 6502 CPU

cpu verilog hdl 6502 6502-processor 6502-emulation

Updated Nov 3, 2018
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kurtjd / hack-computer

My implementation of the Hack computer in HDL as well as software tools such as an assembler, compiler and emulator written in C.

hardware assembly assembler hdl machine-language hack-computer digitallogic

Updated Jun 17, 2022
C

niedzielski / swankmania

Graphics processor and ACX705AKM LCD driver hardware implementation and misc.

game fpga gpu verilog hdl

Updated Dec 9, 2012
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MuratovAS / simpleVCD

Simple TUI viewer for VCF files. Verilog simulation visualization tool.

fpga simulation tui verilog hdl vcd icarus

Updated Nov 8, 2021
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josnelihurt / fpga-stuff

fpga verilog hdl

Updated Oct 29, 2019
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akarxxx1030 / TapeoutSzn

The road to tapeout is real. Welcome to my assignment hub! Physical Design w/ASICs Aug-Dec'23

architecture riscv hdl rtl-gds

Updated Nov 26, 2023
C

kagandikmen / V-FRONT

Where it all begins: Five-stage 32-bit RISC-V CPU in Verilog (Educational, RV32I 2.1 compliant, Zicsr, Zifencei)

embedded cpu processor riscv verilog microprocessor hdl risc-v

Updated Jul 1, 2025
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denporras / CE3201-TrainController

En este laboratorio se requiere que el grupo de trabajo diseñe, implemente en un HDL y demuestre su funcionamiento con un kit FPGA, un controlador para un sistema de dispositivos de señalización y prevención (semáforo y agujas) para un cruce de vía vehicular - ferroviaria . Este controlador estará basado en una máquina de estados finitos (FSM), …

fpga verilog finite-state-machine xilinx hdl spartan

Updated Sep 22, 2017
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pboechat / ice40up5k_riscv

RISC-V SoC on the iCE40UP5K.

firmware riscv verilog hdl soc risc-v picorv32 fpga-programming lattice-fpga picorv

Updated Apr 28, 2025
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Man2Dev / Computer-Architecture-course

Some of my Computer Architecture projects

university mips vhdl xilinx computer-architecture hdl xilinx-ise university-coursework vhdl-code university-projects xilinx-ise-design-suite

Updated Dec 27, 2023
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jasson-chen-git / Learning-Verilog-SystemVerilog

Learning Verilog/SystemVerilog

verilog systemverilog hdl

Updated Sep 14, 2024
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Man2Dev / Logic-Circuits-and-Computer-Architecture-Lab-course

Some of my Logic Circuits and Computer Architecture Lab projects

university mips logic university-project xilinx hdl university-course xilinx-ise university-assignment xilinx-ise-design-suite

Updated Jan 19, 2024
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