Test suite designed to check compliance with the SystemVerilog standard.
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Nov 11, 2025 - SystemVerilog
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hdl
Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.
Here are 105 public repositories matching this topic...
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
cmake asic fpga cpp verification rtl verilog xilinx vivado systemverilog systemc unit-tests hdl modelsim uvm verilator quartus testing-rtl
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Nov 25, 2019 - SystemVerilog
JSilicon: A dual-mode 8-bit CPU core designed entirely from scratch by an AI major during mandatory military service in South Korea. This open-source Verilog project proves that real silicon design — from ALU to CPU architecture — is possible even under the most extreme constraints.
asic rtl verilog finite-state-machine uart alu hdl verilog-hdl open-source-hardware serial-communication rtl-design digital-designs 8bit-cpu chip-design tinytapeout control-logic prototype-core embedded-core minimal-cpu-core
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Oct 19, 2025 - SystemVerilog
DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
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Apr 8, 2024 - SystemVerilog
tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog
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Jul 14, 2021 - SystemVerilog
Fixed point math library for SystemVerilog
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Nov 14, 2024 - SystemVerilog
100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector mealy Moore
makefile verilog synthesis systemverilog hdl testbench systemverilog-hdl systemverilog-simulation rtl-design systemverilog-test-bench edge-detector-with-mealy
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Nov 6, 2022 - SystemVerilog
An open source, parameterized SystemVerilog digital hardware IP library
asic fpga hardware ip verilog systemverilog hardware-designs hardware-libraries hdl digital-design asic-library fpga-library
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May 26, 2024 - SystemVerilog
SystemVerilog Logger
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Sep 30, 2025 - SystemVerilog
A multi-cycle processor designed according to the instruction set(assembly language) of RISC-V using the System Verilog HDL
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Jun 5, 2023 - SystemVerilog
Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster
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Oct 14, 2021 - SystemVerilog
Synthesizable SystemVerilog IP-Core of the I2S Receiver
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Jun 7, 2020 - SystemVerilog
SystemVerilog HDMI encoder, serializer & PLL generator. Tested on Cyclone IV-E, Compatible with Quartus 13.0 through Quartus Prime 20.1.
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Sep 5, 2021 - SystemVerilog
Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis
sdk fpga hardware accelerator matrix project matrix-multiplication verilog xilinx vivado systemverilog hardware-designs hdl hardware-acceleration zynq-7000 systolic-arrays pynq-z2 vitis
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Feb 16, 2024 - SystemVerilog
YM2149 / AY-3-8910 Programmable Sound Generator in SystemVerilog and Verilog. Offers dual PSGs, programmable stereo mixer with bass and treble controls, standard I2S 44.1KHz or 48KHz 16-bit digital audio out, and built-in floating point system clock divider/generator.
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Sep 8, 2022 - SystemVerilog
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