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hdl

Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.

Here are 229 public repositories matching this topic...

analogdevicesinc / hdl

HDL libraries and projects

fpga verilog hdl hacktoberfest analog-devices jesd204b

Updated Nov 7, 2025
Verilog

dpretet / async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

asic fpga async verification verilog synthesis icarus-verilog fifo cdc hdl verilog-hdl fifo-queue fifo-cache verilator asic-design cross-clock-domain

Updated Sep 16, 2025
Verilog

viduraakalanka / HDL-Bits-Solutions

This is a repository containing solutions to the problem statements given in HDL Bits website.

verilog hdl

Updated Jul 16, 2023
Verilog

furrtek / SiliconRE

Traces, schematics, and general infos about custom chips reverse-engineered from silicon

asic fpga arcade-game video-game reverse-engineering arcade verilog chip konami hdl silicon cpld repro taito decap gate-array standard-cell

Updated Nov 4, 2025
Verilog

1801BM1 / cpu11

Revengineered ancient PDP-11 CPUs, originals and clones

engineering verilog reverse retrocomputing hdl pdp-11 cpucore

Updated Oct 22, 2025
Verilog

fomu-workshop

im-tomu / fomu-workshop

Support files for participating in a Fomu workshop

fpga vhdl chisel riscv verilog hdl litex migen fomu fomu-workshop

Updated Mar 17, 2024
Verilog

hell03end / verilog-uart

Simple 8-bit UART realization on Verilog HDL.

fpga verilog uart hdl quartus

Updated Apr 27, 2024
Verilog

WilsonChen003 / HDLGen

HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve

python automation asic script perl rtl verilog hdl soc

Updated Oct 31, 2023
Verilog

adibis / DDR2_Controller

DDR2 memory controller written in Verilog

ddr verilog hdl verilog-project

Updated Feb 28, 2012
Verilog

trcwm / Speech256

An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.

fpga speech synthesizer verilog hdl retrochallenge

Updated May 2, 2019
Verilog

janschiefer / verilog_spi

A simple Verilog SPI master / slave implementation featuring all 4 modes.

asic fpga verilog spi hdl fpgas spi-master spi-slave

Updated Dec 7, 2020
Verilog

ashishrana160796 / verilog-starter-tutorials

Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.

practice embedded-systems verilog up-for-grabs circuit switches beginner-friendly logic-gates hdl verilog-hdl iverilog verilog-snippets verilog-programs verilog-project

Updated Nov 25, 2020
Verilog

JeffDeCola / my-verilog-examples

A place to keep my synthesizable verilog examples.

simulator asic fpga hardware waveform verilog xilinx synthesis vivado systemverilog gtkwave hdl iverilog hardware-description-language verilog-simulator asic-design synthesize hardware-architecture

Updated Apr 20, 2025
Verilog

sam210723 / fpga

Collection of projects for various FPGA development boards

fpga verilog icestudio hdl vga vga-driver tinyfpga-bx colorlight tinyfpga 5a-75b icesugar icesugar-nano mimas-v2

Updated May 13, 2024
Verilog

Yvan-xy / verilog-doc

All About HDL

verilog hdl hdlbits verilog-doc

Updated Aug 21, 2019
Verilog

WangXuan95 / FPGA-QOI

An FPGA-based QOI image compressor and decompressor in Verilog. 基于FPGA的QOI图像压缩器和解压器。

compression fpga rtl verilog image-compression systemverilog hdl qoi

Updated Sep 18, 2024
Verilog

matt-alencar / fpga-uart-tx-rx

Basic UART TX/RX module for FPGA

fpga verilog uart hdl uart-protocol soft-core uart-interface

Updated Oct 18, 2018
Verilog

jiegec / fpu-wrappers

Wrappers for open source FPU hardware implementations.

chisel3 hdl spinalhdl fpu

Updated Apr 10, 2024
Verilog

adibis / Interrupt_Controller

An 8 input interrupt controller written in Verilog.

verilog hdl verilog-components verilog-project

Updated Mar 22, 2012
Verilog

buhe / bugu-computer

💻 Build own computer by fpga.

fpga tutorials verilog nand2tetris hdl own

Updated Jun 9, 2022
Verilog

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Wikipedia: Wikipedia